隨著積體電路製造技術的演進以及設計逐漸趨向複雜，電壓壓降效應在決定設計電路之效能和可靠性上變成是一個重要的因素。有許多電壓壓降分析技術藉由電流源模型被提出來用以分析電壓壓降效應。然而，以電流源為基礎之模型會根據電流波型之近似準確程度影響電壓壓降效應分析的精確度。
本地電荷分享效應以及電流與電壓壓降之關係的效應，此兩種效應會影響電壓壓降分析。因此，在以電流源為基礎之模型下，忽略此二效應會導致電壓壓降分析之不準確。
本論文著重於在電流源為基礎之模型下的電流波型近似和模擬造成電壓壓降之二種效應。核心技術是在電力網路應用電流源、開關以及基礎電路元件來增進高準確度之電壓降分析。
實驗中使用ISCAS85標準電路來驗證本篇論文所提出之技術之準確度。考慮二效應之單元模型技術在低電壓壓降電路上能夠提供較低的錯誤率以及差異性。

As the process technologies continue to shrink and design complexity increases, the IR-drop effect becomes an important factor determining the performance and reliability of a design. Several IR-drop analysis techniques have been proposed to address this issue by current-based modeling. The accuracy of IR-drop analysis depends on the quality of the current waveform approximation. Two effects can influence IR-drop analysis, that is, the local charge sharing effect and the relation between gate current and IR-drop effect. Ignoring these two effects in current-based modeling induce inaccuracy in IR-drop analysis.
This thesis focuses on the current waveform approximation and modeling the two effects impacting IR-drop. The core technology is applying current source, switches and fundamental circuit components on power network to improve the accuracy of IR-drop analysis.
The accuracy of the proposed technique is validated on ISCAS85 benchmark circuits. The proposed technique concerning two effects together achieves higher accuracy when test circuit suffering less severe IR-drop.

摘要 III
ABSTRACT IV
CONTENTS V
LIST OF FIGURES VI
LIST OF TABLES VII
1. INTRODUCTION 1
2. PRELIMINARIES 5
2.1. CURRENT-BASED MODELING TECHNIQUE 5
2.2. TWO IR-DROP IMPACT EFFECTS 9
2.2.1. Local Charge Sharing Effect 9
2.2.2. The Relation with Current and IR-drop effect 10
3. PROPOSED TECHNIQUE 12
3.1. NEW CURRENT BASED MODEL 12
3.2. TWO IR-DROP IMPACT EFFECT MODELING 17
3.2.1. Local Charge Sharing effect 18
3.2.2. The Relation with Current and IR-drop effect 23
3.3. CELL CHARACTERIZATION 25
3.4. IR-DROP ANALYSIS FLOW 27
3.4.1. Circuit Describing File 29
3.4.1.1. Spice Netlist FILE 29
3.4.1.2. Spice Circuit File 29
3.4.1.3. Input Cap of Netlist 31
3.4.1.4. Transition Fault Pattern 31
3.4.2. Switching Event 32
3.4.2.1. Hspice-Based Event List 33
3.4.2.2. VCD-Based Event List 36
4. EXPERIMENTAL RESULTS 38
4.1. PROPOSED CELL MODEL V.S. REFERENCE CELL MODEL 42
4.2. PROPOSED TECHNIQUE W/O COMPENSATED EFFECT V.S. WITH COMPENSATED EFFECT 46
4.3. PROPOSED TECHNIQUE W/O COMPENSATED EFFECT V.S. WITH EFFECTS TOGETHER 52
4.4. PROPOSED TECHNIQUE WITH HSPICE BASED V.S. VCD BASED TIMING INFORMATION 56
5. DISCUSSION 60
6. CONCLUSION 62
7. REFERENCE 63

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