本文首先介紹二階三角積分調變器(2-order Σ ADC)的基本原理，和此電路的特性及噪音塑形(noise-shaping)所帶來的影響。接著探討二階三角積分調變器使用多位元的架構後，所帶來的線性誤差對於電路解析影響，最後本文設計一個適用於多輸入多位元的二階三角積分調變器的動態元件匹配架構，以降低多位元的類比數位轉換器在不匹配所產生的線性誤差。本文所提出的樹狀架構和DWA，相較於傳統樹狀架構可以降低3-bit DAC 元件不匹配所產生的線性誤差，同時SNR 也提高了45dB。

This paper first described the basic principle and the characteristics of the second-order sigma-delta modulator (SDM), and the influence of noise-shaping on SDM. Then, we studied the linearity error caused by the influence of the circuit's resolution about the architecture of second-order SDM with multi-bit.
This paper developed a dynamic element match structure for a multi-input multi-bits second-order sigma-delta converter. The mismatch noise of an analog-to-digital converter can be reduced. Simulation results show that the new structure is better than conventional tree structure for decreasing mismatch noise of a 3-bit DAC and increasing its SNR value in 45dB.

摘要.............................................................................................................................iv
Abstract........................................................................................................................v
目 錄....................................................................................................................... vii
表 目 錄.................................................................................................................ix
圖 目 錄..................................................................................................................x
第一章 序論.................................................................................................................1
1.1 研究背景和目的............................................................................................1
第二章 Σ ADC 的基本原理.......................................................................................3
2.1 二階Σ- ADC 基本原理...............................................................................3
2.2 噪音塑形的效果............................................................................................4
2.3 單一位元Σ- ADC 和三位元Σ- ADC 的比較.............................................5
第三章、一位元Σ- ADC 的模擬實驗.......................................................................7
3.1 ㄧ位元Σ- ADC 的動作確認........................................................................7
3.2 SNDR 的計算方法..........................................................................................8
3.2.1 由頻域計算SNDR ..............................................................................8
3.2.2 由時域計算SNDR ..............................................................................9
3.2.3 積分器中OP 放大器的增益討論......................................................12
第四章 多輸入Σ- ADC 的討論..............................................................................15
4.1 輸入訊號經由開關切換對Σ- ADC 影響..................................................15
4.2 傳統多輸入Σ- ADC..................................................................................16
4.3 新式多輸入Σ- ADC...................................................................................18
4.4 新式多輸入Σ- ADC 的積分器架構..........................................................19
第五章 多輸入Σ- ADC 的模擬實驗......................................................................20
5.1 傳統多輸入Σ- ADC..................................................................................20
5.2 新式多輸入Σ- ADC...................................................................................21
5.3 開關切換頻率和SNDR 的關係....................................................................23
5.4 三位元二輸入Σ- ADC ..............................................................................25
第六章 含有DAC 線性誤差的Σ- ADC .................................................................28
6.1 DAC 線性誤差的影響..................................................................................28
6.2 改善DAC 線性誤差....................................................................................31
6.2.1 DER（Dynamic Element Randomization）........................................32
6.2.2 DWA（Data Weighted Averaging）....................................................33
6.2.3 Tree Structure......................................................................................37
第七章 用於多輸入多位元Σ- ADC 的DEM.........................................................42
7.1 用於多輸入多位元Σ- ADC 的新式DWA................................................42
7.2 用於多輸入多位元Σ- ADC 的新式Tree Structure...................................45
第八章 總結...............................................................................................................51
參考文獻....................................................................................................................52

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