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研究生:洪偉翔
研究生(外文):Wei-hsiang Hung
論文名稱:多輸入多位元三角積分調變器的DEM設計
論文名稱(外文):The Design of a DEM Architecture for Multi-Input and Multi-Bit Sigma-Delta Converters
指導教授:黎靖黎靖引用關係
學位類別:碩士
校院名稱:南台科技大學
系所名稱:電子工程系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2010
畢業學年度:98
語文別:中文
論文頁數:65
中文關鍵詞:三角積分調變器動態元件匹配
外文關鍵詞:Dynamic Element MatchSigma-delta ADC
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本文首先介紹二階三角積分調變器(2-order Σ ADC)的基本原理,和此電路的特性及噪音塑形(noise-shaping)所帶來的影響。接著探討二階三角積分調變器使用多位元的架構後,所帶來的線性誤差對於電路解析影響,最後本文設計一個適用於多輸入多位元的二階三角積分調變器的動態元件匹配架構,以降低多位元的類比數位轉換器在不匹配所產生的線性誤差。本文所提出的樹狀架構和DWA,相較於傳統樹狀架構可以降低3-bit DAC 元件不匹配所產生的線性誤差,同時SNR 也提高了45dB。
This paper first described the basic principle and the characteristics of the second-order sigma-delta modulator (SDM), and the influence of noise-shaping on SDM. Then, we studied the linearity error caused by the influence of the circuit's resolution about the architecture of second-order SDM with multi-bit.
This paper developed a dynamic element match structure for a multi-input multi-bits second-order sigma-delta converter. The mismatch noise of an analog-to-digital converter can be reduced. Simulation results show that the new structure is better than conventional tree structure for decreasing mismatch noise of a 3-bit DAC and increasing its SNR value in 45dB.
摘要.............................................................................................................................iv
Abstract........................................................................................................................v
目 錄....................................................................................................................... vii
表 目 錄.................................................................................................................ix
圖 目 錄..................................................................................................................x
第一章 序論.................................................................................................................1
1.1 研究背景和目的............................................................................................1
第二章 Σ ADC 的基本原理.......................................................................................3
2.1 二階Σ- ADC 基本原理...............................................................................3
2.2 噪音塑形的效果............................................................................................4
2.3 單一位元Σ- ADC 和三位元Σ- ADC 的比較.............................................5
第三章、一位元Σ- ADC 的模擬實驗.......................................................................7
3.1 ㄧ位元Σ- ADC 的動作確認........................................................................7
3.2 SNDR 的計算方法..........................................................................................8
3.2.1 由頻域計算SNDR ..............................................................................8
3.2.2 由時域計算SNDR ..............................................................................9
3.2.3 積分器中OP 放大器的增益討論......................................................12
第四章 多輸入Σ- ADC 的討論..............................................................................15
4.1 輸入訊號經由開關切換對Σ- ADC 影響..................................................15
4.2 傳統多輸入Σ- ADC..................................................................................16
4.3 新式多輸入Σ- ADC...................................................................................18
4.4 新式多輸入Σ- ADC 的積分器架構..........................................................19
第五章 多輸入Σ- ADC 的模擬實驗......................................................................20
5.1 傳統多輸入Σ- ADC..................................................................................20
5.2 新式多輸入Σ- ADC...................................................................................21
5.3 開關切換頻率和SNDR 的關係....................................................................23
5.4 三位元二輸入Σ- ADC ..............................................................................25
第六章 含有DAC 線性誤差的Σ- ADC .................................................................28
6.1 DAC 線性誤差的影響..................................................................................28
6.2 改善DAC 線性誤差....................................................................................31
6.2.1 DER(Dynamic Element Randomization)........................................32
6.2.2 DWA(Data Weighted Averaging)....................................................33
6.2.3 Tree Structure......................................................................................37
第七章 用於多輸入多位元Σ- ADC 的DEM.........................................................42
7.1 用於多輸入多位元Σ- ADC 的新式DWA................................................42
7.2 用於多輸入多位元Σ- ADC 的新式Tree Structure...................................45
第八章 總結...............................................................................................................51
參考文獻....................................................................................................................52
[1] F. Op’t Eynde and W. Sansen, Analog Interfaces for Digital Signal Processing System. Boston: Kluwer Academic Publishers, 1993.
[2] P. M. Aziz, H. V. Sorensen, and J. V. D. Spiegel, “An Overview of Sigma-Delta Converters,” IEEE Signal Processing Magazine, Vol. 13, No. 1, pp. 61-84, Jan.1996.
[3] R. Schreier and G. C. Temes, Understanding Delta-Sigma Data Converters, Wiley,2005.
[4] I. J. O’Connell and C. Lyden, “A Novel Noise Efficient Feedback DAC within a Switched Capacitor Σ ADC,” IEEE Transactions on Circuits and Systems, Vol.52, No. 1, pp. 71-78, Jan. 2005.
[5] Y. Fujimoto, P. Lo Re, and M. Miyamoto, “A Delta-Sigma Modulator for a 1-bitDigital Switching Amplifier,” IEEE Journal of Solid-State Circuits, Vol. 40, No. 9, pp. 1865-1871, Sept. 2005.
[6] I. H. Jorgensen, “A 3rd Order Low Power SI Σ -A/D Converter for Voice-Band Application,” IEEE International Symposium on Circuits and System, pp. 69-72,Jun. 1997.
[7] J. Candy and G. Temes, Oversampling Delta Sigma Data Converter. Now York:IEEE Press, 1997.
[8] S. R. Norsworthy, R. Schreier, and G. C. Temes, Delta-Sigma Data Converters: Theory, Design, and Simulation, Wiley-IEEE Press, Oct 1996.
[9] F. Medeiro, Top-Down Design of High-Performance Sigma-Delta Modulators, Kluwer Academic, 1999.
[10] H. Inose, Y. Yasada, and J. Murakami, “A Telemetering System by Code Modulation--△-Σ Modulation,” IRE Trans. Space Electron. And Telemetry, Vol. SET-8, pp. 204-209, Sept. 1962.
[11] S. R. Norsworthy, I. G. Post, and H. S. Fetterman, “A 14-bit 80-KHz Sigma-Delta A/D Converter: Modeling, Design, and Performance Evaluation,” IEEE Journal of Solid-State Circuits, Vol. 24, No. 2, pp. 256-266, Apr. 1989.
[12] S.-H. Mona and G. W. Roberts, “Low Power Delta-Sigma Modulator for ADSL Applications in a Low–Voltage CMOS Technology,” IEEE Transactions on Circuit and Systems, Vol. 52, No. 10, pp. 2075-2089, Oct. 2005.
[13] T.-S. Lee, W.-B. Lin, and D.-L. Lee, “Design Techniques for Low-Voltage Micropower CMOS Switched-Capacitor Delta-Sigma Modulator,” IEEE Midwest Symposium on Circuits and Systems, Vol. 3, pp. 331-334, July 2004.
[14] C. R. T. D. Mori, P. C. Crepaldi, and T. C. Pimenta, “A 3-V 12-bit Second Order Sigma-Delta Modulator Design in 0.8-μm CMOS,” 14th Symposium on Integrated Circuits and Systems Design, pp. 124-129, Sept. 2001.
[15] S.-H. Yu and J.-S. Hu, “Analysis and Design of 1-bit Noise-shaping Quantizer Using Variable Structure Control Approach,” IEEE American Control Conference, Vol. 2, pp. 1271-1276, June 30-July 2, 2004.
[16] E. Hosseinzadeh, J. Belzile, and C. Thibeault, “VLSI Implementation of a High Speed Second Order Sigma-Delta Modulator with High-Performance Integrators,” IEEE Canadian Conference on Electrical and Computer Engineering, Vol. 2, pp.545-548, May 1998.
[17] J.-S. Chiang, T.-H. Chang and P.-C. Chou, “A Novel Wideband Low-Distortion Cascaded Sigma-Delta ADC,” IEEE International Symposium on Circuits and System, Vol. 2, pp. 636-639, May 2002.
[18] J. Silva, U. Moon, J. Steensgaard, and G. C. Temes, “Wideband Low-Distortion Delta-Sigma ADC Topology,” IEEE Electronic Letters, Vol. 37, No. 12, pp.737-738, June 2001.
[19] A. A. Hamoui and K. Martin, “Delta-Sigma Modulator Topologies for High-Speed High-Resolution A/D Converters,” IEEE 45th Midwest Symposium on Circuits and Systems, Vol. 1, pp. 356-359, Aug. 2002.
[20] Y. Zhang, E. Hayahara, S. Hirano, and N. Sakakibara, “An Optimal Design Consideration for High-Order Delta-Sigma A/D Converter,” IEEE Asia-Pacific Conference on Circuits and Systems, pp. 309-312, Dec. 2000.
[21] R. W. Adams, P. R. Ferguson, Jr. A. Ganesan, S. Vincelette, A. Volpe, and R. Libert, “Theory and Practical Implementation of a Fifth-Order Sigma-Delta A/D converter,” J. Audio Eng. Soc., Vol. 39, No. 7/8, pp.515-528, July 1991.
[22] P. R. Ferguson, Jr., A. Ganesan, and R. W. Adams, “One-Bit Higher OrderSigma-Delta A/D Converters, ” Proc. ISCAS, pp. 890-893, May 1990.
[23] K. C-H. Chao, S. Nadeem, W. L. Lee, and C. G. Sodini, “A Higher Order Topology for Interpolative Modulators for Oversampling A/D Converters,” IEEETrans. Circuit Syst. Vol. CAS-37, No. 3 , pp. 309-318, Mar. 1990.
[24] J. Silva, U. Moon, and G. C. Temes, “Low-Distortion Delta-Sigma Topologies for MASH Architectures,” IEEE International Symposium on Circuits and System, pp.1144-1147, 2004.
[25] L. A. Williams III and B. A. Wooley, “A Third-Order Sigma-Delta Modulator with Extended Dynamic Range,” IEEE J. Solid-State Circuits, Vol. 29, No. 3, pp.193-202, Mar. 1994.
[26] G. Yin, F. Stubbe, and W. Sansen, “A 16-bit 320-KHz CMOS A/D Converter Using Two-Stage Third Order Σ Noise Shaping,” IEEE J. Solid-State Circuit, Vol.28, No. 6, pp. 640-647, June 1993.
[27] R. T. Baird and T. S. Fiez, “Stability Analysis of High-Order Delta Sigma Modulators for ADCs,” IEEE Trans. Circuit Syst. II, Vol. 41, No. 1 , pp.59-62, Jan.1994.
[28] T. Ritoniemi, T. Karema, and H. Tenhunen, “Design of Stable High Order 1-Bit Sigma-Delta Modulators,” IEEE International Symposium on Circuits and System, Vol. 4, pp. 3267-3270, May 1990.
[29] I. Galton, “Spectral Shaping of Circuit Errors in Digital-to-analog Converters,” IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 44, no. 10, pp. 808-817, Oct 1997.
[30] L. R. Carley, “A Noise Shaping Coder Topology for 15-bit Converters,” IEEE J. Solid-State Circuits, Vol. SC-24, No. 2 , pp. 267-275, Apr. 1989.
[31] R. Schreier and G. C. Temes, Understanding Delta-Sigma Data Converters, IEEE Press, 2005.
[32] T.-C. Hsueh, “The Design and Implementation of Low-Pass Multibit Delta-Sigma Modulators,” Master thesis, National Taiwan University, Jun. 2001.
[33] S. Matumoto, M. Hotta, “Multi-input Sigma-Delta A/D Converter,” 2008 IEEJInt'l Analog VLSI Workshop .
[34] O. Nys and R. K. Henderson , “A 19-bit Low Power Multibit Sigma-Delta ADCBased on Data Weighted Averaging,” IEEE J. Solid-State Circuits, Vol. 32, No. 7,pp. 933-942, July 1997.
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