臺灣博碩士論文加值系統

本篇論文主要描述一個低功率、10位元、操作頻率在10MHz而工作電壓在1V的管流式類比數位轉換器之設計，並提出利用切換式運算放大器共享技術來減少轉換器元件數量。有別於一般的低功率低電壓電路，本架構不需要過多的運算放大器，單純利用開關切換以降低功率以及達成運算放大器共用。本轉換器採用標準0.18um 1P6M CMOS製程，並透過Hspice模擬電路架構。本轉換器操作在10MHz的取樣頻率，工作電壓為1V，輸入頻率為530kHz下SNDR為51.66dB，其總功率消耗為18mW。

In this thesis, a 10-bit 10-MHz pipelined analog-to-digital converter (ADC) consisting of 1.5-bit/stage has been designed and verified by Hspice simulation with TSMC 0.18-µm 1P6M CMOS process models. In order to operation at 1V, the switched-opamp technique is employed in the pipelined ADC. In order to saving the power consumption and chip area, the analog-to-digital converter merges two output stages using an opamp-sharing technique.
The resulting peak signal-to-noise and distortion ratio (SNDR) of the pipelined ADC is 51.66 dB with sampling frequency of 10 MHz at input frequency of 530 kHz. Power consumption of this ADC is 18mW with 1V power supply.

誌謝 i
ABSTRACT ii
摘要 iii
TABLE OF CONTENTS iv
LIST OF FIGURES vii
CHAPTER 1 INTRODUCTION 1
1.1 Motivation and Goal 1
1.2 Organization 3
CHAPTER 2 PIPELINED A/D CONVERTER 5
2.1 Introduction 5
2.2 Pipelined ADC 5
2.2.1 Digital Error Correction Technique 8
2.2.2 1.5Bit/Stage for Pipelined ADC 11
2.3 Summary 12
CHAPTER 3 THE DESIGN OF LOW-VOLTAGE PIPELINED ANALOG-TO-DIGITAL CONVERTER 13
3.1 Introduction 13
3.2 Switched-Capacitor Circuit in Low-Voltage 13
3.2.1 Conventional SC MDAC Circuit 14
3.2.2 Problem at Low-Voltage SC Circuit 15
3.2.3 Charge-Pump Clock Driver 17
3.2.4 Clock Bootstrapped Switch 18
3.2.5 Low-Threshold Voltage Process 19
3.2.6 Principle of Switched-Opamp Technique 20
3.2.7 Opamp-Sharing Technique 21
CHAPTER 4 DESIGN OF PIPELINED ADC 23
4.1 Specification of Pipelined ADC 23
4.1.1 The Required Minimum Capacitor Size 24
4.1.2 Specification of Opamp 26
4.2 Low-Voltage Sample-and-Hold Circuit 28
4.3 Design of So-MDAC with Opamp-Sharing 30
CHAPTER 5 CIRCUIT DESIGN AND SIMULATION RESULTS 36
5.1 Design and Simulation of the Opamp 36
5.1.1 Opamp Design 36
5.1.2 Switched-Capacitor CMFB 40
5.1.3 Simulation of The Opamp 43
5. 2 Sub-ADC 44
5. 3 Simulation of The Proposed Low-Voltage Pipelined ADC 47
CHAPTER 6 CONCLUSION 51
6. 1 Conclusion 51
6. 2 Future Work 51
REFERENCES 53

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