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研究生:黃天佑
研究生(外文):Tien-yu Huang
論文名稱:具適應性演算之全數位鎖相迴路
論文名稱(外文):ALL DIGITAL PHASE-LOCKED LOOP WITH ADAPTIVE SEARCHING ALGORITHM
指導教授:劉皆成
指導教授(外文):Jie-cherng Liu
學位類別:碩士
校院名稱:大同大學
系所名稱:通訊工程研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2010
畢業學年度:98
語文別:英文
論文頁數:73
中文關鍵詞:適應性全數位鎖相迴路
外文關鍵詞:ADPLLAdaptive
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由於傳統類比式鎖相迴路在電源穩定度,雜訊干擾以及設計困難度等方面上的缺點,全數位式鎖相迴路比起傳統鎖相迴路可提供更好的成效。全數位式鎖相迴路在設計上具有可程式化以及可攜式等優點,故其可有效率減少在其它設計過程中之設計困難度。
本論文實現一個全數位式鎖相迴路,其控制單元使用一種搜尋式演算法可操作在高頻率解析度下,而此演算法提供快速追蹤的搜尋指令可進一步降低鎖上所需花費的時間。此全數位式鎖相迴路以MATLAB Simulink 模擬實現,其模擬結果顯示當DCO操作頻率在0.8GHz-1.4GHz之間,參考訊號為134MHz時,其鎖上時間所需花費的時間為1.5μs; 當DCO操作頻率在1.2GHz-4.35GHz之間,參考訊號為300MHz時,其鎖上時間所需花費的時間則為0.9μs.
Due to the disadvantages of the traditional analog phase-locked loop (APLL) over source stability, noise interference and design difficulty, the all digital phase-locked loop (ADPLL) can provide better performance than the traditional PLL. The ADPLL is programmable and portable over design that it can efficiently reduce the difficulties in other design process.
This thesis implements an ADPLL with a searching algorithm in its control unit that can perform in high frequency resolutions, and the algorithm provides fast tracking search step to further reduce the lock in time. The ADPLL is simulated with the MATLAB Simulink, and the simulation result shows that when the DCO operating in 0.8GHz-1.4GHz, the lock in time of the reference clock for 134MHz is 1.5μs; when the DCO operating in 1.2GHz-4.35GHz, the lock in time of the reference clock for 300MHz is 0.9μs.
ACKNOWLEDGEMENTS I
ABSTRACT II
摘要 III
TABLE OF CONTENTS IV
LIST OF FIGURES VI
CHAPTER 1 Introduction 1
1.1 Motivation 1
1.2 Thesis Organization 2
CHAPTER 2 Phase-Locked Loops Overview 3
2.1 PLL Background Study 3
2.2 Basic Concept of PLL 3
2.3 Analog PLL (APLL) 6
2.4 Digital PLL (DPLL) 7
2.5 All-Digital PLL (ADPLL) 8
2.6 Software PLL (SPLL) 9
2.7 Delay-Locked Loop (DLL) 11
CHAPTER 3 Circuit Design of ADPLL Structure 12
3.1 The Concept of Structure and Architecture 12
3.2 Phase Frequency Detector 13
3.3 Digitally Controlled Oscillator 18
3.4 Controlled Algorithm 25
3.5 Loop Filter 29
CHAPTER 4 Implementation of ADPLL Using MATLAB Simulink 30
4.1 Overall 30
4.2 Circuit Implementation of PFD 30
4.3 Circuit Implementation of DCO 37
4.4 System Controller 39
4.4.1 Frequency Acquisition 41
4.4.2 Phase Acquisition 43
4.4.3 Phase Maintenance 45
4.4.4 Hardware Implementation 47
4.5 Implementation of Loop Filter 48
4.6 Simulation Results of the ADPLL 51
CHAPTER 5 CONCLUSIONS 61
REFERENCES 62
[1] D. Richman, “Color-Carrier Reference Phase Synchronization and Accuracy in NTSC Color Television,” Proceedings IRE, vol. 42, pp. 106-133, January 1954.
[2] H.T. McAleer, “A New Look at the Phase-Locked Oscillator,” Proceedings of the IRE, vol. 47, no. 6, pp. 1137-1143, June 1959.
[3] D. R. Stephens, Phase-Locked Loops for Wireless Communications: Digital, Analog and Optical Implementations. Kluwer Academic Publishers, 2002.
[4] C. C. Wang, A digital frequency synthesizer HDL generator for SOC design. M.S. Thesis, National Chiao-Tung University, 2000.
[5] T. Y. Hsu, B. J. Shieh, and C. Y. Lee, “An all digital phase locked loop (ADPLL) based clock recovery circuit,” IEEE Journal of Solid-State Circuits, vol. 34, no. 8, pp. 1063-1073, August 1999.
[6] C. C. Chung and C. Y. Lee, “An All-Digital Phase-Locked Loop for High-Speed Clock Generation,” IEEE Journal of Solid-State Circuits, vol. 38, no. 2, February 2003.
[7] R. E. Best, Phase-Locked Loops: Design, Simulation, and Applications. McGraw-Hill Professional, 1999.
[8] C. C. Chen, The Analysis and Design of All-Digital Phase-Locked Loop (ADPLL). M.S. thesis, National Chiao-Tung University, 2001.
[9] T. Y. Hsu, The study of All Digital Phase-Locked Loop (ADPLL) and its Applications. PhD thesis, National Chiao-Tung University, 1999.
[10] J. Dunning, G. Garcia, J. Lundberg, and E. Nuckolls, “An All-Digital Phase-Locked Loop with 50-Cycle Lock Time Suitable for High-Performance Microprocessors,” IEEE Journal of Solid-State Circuits, vol. 30, no. 4, April 1995.
[11] W. F. Egan, Phase-Lock Basics. John Wiley & Sons, Inc., 2008.
[12] F. M. Gardner, Phaselock Techniques. John Wiley & Sons, Inc., 2005.
[13] S. S. Tsai, All Digital Wide Frequency Range Low Cost Delay-Locked Loop. National Chiao-Tung University.
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