臺灣博碩士論文加值系統

有鑑於傳統USB2.0傳輸架構之中擁有需要外接石英震盪器來當作參考時脈以及依靠以多相位產生器來完成資料回復等技術會造成額外面積成本以及功率消耗的問題；本論文提出一個不需要外部參考時脈之資料與時脈回復電路，此電路用於USB2.0通訊系統之接收端，針對傳送端傳送過來的USB2.0封包內之同步訊號區段來完成接收端與傳送端時脈之頻率追蹤及相位鎖定，使得接收端可正確的將傳送端傳送過來的資料重現於接收端之暫存器內；但由於USB2.0之同步訊號為一個有限的長度（高速模式下為32位元，全速及低速模式中為7位元），為了滿足此快速鎖定的需求，本論文提出了內嵌時間至數位轉換器之振盪器使得本電路在頻率追蹤上可在一個同步訊號的時間即可快速的鎖定至接近於資料傳送率的頻率區段，使之加快追蹤過程讓整體鎖定時間可於同步訊號的區段之內完成。本論文也提出一個雙模式相位與頻率偵測器，可於封包中的同步訊號區段使用頻率偵測模式來達成頻率追蹤，於隨機資料的區段中可切換至相位偵測模式，來達成並維護接收端振盪器與輸入資料訊號間相位的對齊。
USB2.0之中分別提供三種速度模式，分別為高速模式(480MHz)、全速模式(12MHz) 以及低速模式(1.5MHz)；在傳統USB2.0傳輸架構之中，每一種速度模式下都需要一個與之對應的時脈與資料回復電路造成成本的提升；本論文提出的時脈與資料回復電路能達到以一套硬體完成寬頻的工作範圍來涵蓋USB2.0中所有速度模式以減少硬體成本。為了支援低頻的模式本論文提出了一個低頻時脈合成器減少傳統上使用延遲單元的作法，減少面積並達成寬頻連續速率時脈與資料回復電路來支援於USB 2.0下所有速度模式。
本論文提出之全數位電路使用65奈米製程的標準元件庫實現，工作範圍為700kHz到500MHz可用於連續速率之時脈及資料回復，晶片面積為150m2，其最高功率消耗為運作於500MHz之消耗功率為2.63mW。

The conventional USB2.0 transceiver usually needs the external reference clock and multi-phase scheme for over-sampling architecture and causes the additional cost. To solve this problem, an all-digital fast frequency acquisition full-rate continuous rate clock and data recovery (CDR) circuit for USB 2.0 applications without a reference clock is presented in this thesis. Lock-in time is constrained by the short USB 2.0 packet synchronization pattern’s specifications (32bit for high speed mode and 7bit for full/slow speed mode). Therefore we propose a wide range time-to-digital converter (TDC) embedded digital control oscillator (DCO) to achieve fast frequency acquisition so that the lock-in time can be reduced to satisfy the length of synchronization pattern. A dual mode phase and frequency detector (PFD) is proposed to perform two operating modes in the frequency tracking in the sync pattern region and the phase aligning in the random data pattern region.
In order to support all USB 2.0 speed modes: high speed mode (480MHz), full speed mode (12MHz) and slow speed mode (1.5MHz), the low frequency clock synthesizer is proposed in this thesis. It can achieve the wide range continuous rate clock and data recovery with reduced area cost and cover all the operation modes of USB 2.0.
The proposed ADCDR is implemented on standard performance 65nm CMOS process. The operating range of proposed ADCDR circuit is from 700kHz to 500MHz which covers all speed modes of USB 2.0. The chip size is 644m2 and the core size is 150m2. The power consumption is 2.63 mW at 500MHz.

Chapter 1 Introduction 11
1.1 Conventional CDR circuit survey 11
1.1.1 Basic concept of CDR circuit 11
1.1.1.1 Sample CDR Circuit 11
1.1.1.2 Phase Detector in CDR circuit 12
1.1.2 Multiphase Scheme for CDR circuit 13
1.1.2.1 Reduced-rate oversampling CDR circuit 14
1.1.2.2 Blind oversampling type CDR circuit 15
1.1.3 Modern implementation of CDR circuit 16
1.1.3.1 Single rate CDR circuit 16
1.1.3.2 Multi-rate CDR circuit 16
1.1.3.3 Continuous rate CDR circuit 17
1.1.4 Referenceless issue of CDR circuit 18
1.2 Introduction to USB 2.0 19
1.2.1 USB 2.0 overview 19
1.2.2 USB 2.0 protocol layer 22
1.3 Design challenges of CDR circuit in USB2.0 25
1.4 Summary 27
Chapter 2 Referenceless CDR Circuit for USB2.0 High Speed Mode 28
2.1 System Architecture Overview 28
2.2 Dual Mode Phase and Frequency Detector 31
2.3 Time-to-Digital Converter Embedded DCO 33
2.3.1 Structure 33
2.3.2 MUX Type DCO structure 34
2.3.3 DCV fine-tune delay line 35
2.3.4 Time-to-Digital Converter 36
2.4 Adaptive Gain in Consecutive Identical Digit 38
Chapter 3 Wide Range Improvement of Supporting USB2.0 Full/Low Speed Mode 40
3.1 System Architecture with Wide Operating Range Improvement 40
3.2 Wide Range Cyclic TDC-embedded DCO 42
3.3 Low Frequency Clock Synthesizer 46
3.3.1 Cyclic Delay of low frequency clock synthesization 46
3.3.2 Fast Reset Scheme on DCO 49
Chapter 4 Experimental Results 51
4.1 Test Chip Implementation 51
4.2 Test Chip Measurement Result 54
4.3 Final Chip Implementation 59
4.4 Full Chip Overall Simulation 61
4.5 Bit Error Rate measurement in RTL Behavior Model Simulation 63
4.6 Chip Summary and Comparison Table 65
Chapter 5 Conclusion and Future Works 68
Reference 70

[1]Sang-Hyun Lee, Moon-Sang Hwang, Youngdon Choi, “A 5-Gb/s 0.25-um CMOS Jitter-Tolerant Variable-Interval Oversampling Clock/Data Recovery Circuit,” in IEEE Journal of Solid-State Circuits, Vol. 37, pp. 1822-1830, Dec. 2002.
[2]Sang-Hune Park; Kwang-Hee Choi; Jung-Bum Shin; Jae-Yoon Sim; Hong-June Park, “A Single-Data-Bit Blind Oversampling Data-Recovery Circuit With an Add-Drop FIFO for USB2.0 High-Speed Interface,” in IEEE Transaction on Circuits and System II: Express Briefs, Vol. 55 No. 2, pp. 156-160, Feb. 2008.
[3]Banu, M.; Dunlop, A, “A 660MWs CMOS Clock Recovery Circuit with Instantaneous Locking for NRZ Data and Burst-Mode Transmission,” in Proceeding of IEEE Solid-State Circuits Conference, pp. 102-103, 1993.
[4]“USB 2.0 Transceiver Macrocell Interface(UTMI) Specification,” Intel Corporation, Mar. 2001
[5]USB Implementers Forum, “USB 2.0 specification”, Apr. 2000
[6]Jos´e Sarmento, John T. Stonick, “A Minimal-Gate-Count Fully Digital Frequency-Tracking Oversampling CDR Circuit,” in Proceeding of IEEE International Symposium Circuit and Systems, pp. 2099-2102 , 2010.
[7]Yoshio Miki, Member, IEEE, Tatsuya Saito, Hiroki Yamashita, Fumio Yuki, Takashige Baba, Akio Koyama, and Masahito Sonehara, “A 50-mW/ch 2.5-Gb/s/ch Data Recovery Circuit for the SFI-5 Interface With Digital Eye-Tracking,” in IEEE Journal of Solid-State Circuits, Vol. 39, pp. 613-621, Apr. 2004.
[8]Ming-ta Hsieh, Sobelman, G., “Architectures for Multi-Gigabit Wire-Linked Clock and Data Recovery,” IEEE Circuits and Systems Magazine, Vol. 8, pp. 45-57, 2008
[9]Behzad Razavi, “Challenges in the Design of High-Speed Clock and Data Recovery Circuits,” IEEE Communication Magazine, Vol. 40, pp. 94-101, Aug. 2002
[10] Jaeha Kim and Deog-Kyoon Jeong, “Multi-Gigabit-Rate Clock and Data Recovery Based on Blind Oversampling,” IEEE Communication Magazine, Vol. 41 pp. 68-74, Dec. 2003.
[11]Pao-Lung Chen, Ching-Che Chung, and Chen-Yi Lee, “A Clock Generation with Cascaded Dynamic Frequency Counting Loops for Wide Multiplication Range Applications,” in IEEE Journal of Solid-State Circuits, Vol. 41, pp. 1275-1285, Jun. 2006.
[12]Scheytt, J.C., Hanke, G., Langmann, U., “A 0.155-, 0.622-, and 2.488-Gb/s Automatic Bit-Rate Selecting Clock and Data Recovery IC for Bit-Rate Transparent SDH Systems,” in IEEE Journal of Solid-State Circuits, Vol. 4, pp. 1935-1943, Dec. 1999.
[13]Che-Fu Liang and Shen-luan Liu, “A 20/10/5/2.5Gb/s Power-scaling Burst-Mode CDR Circuit Using GVCO/Div2/DFF Tri-mode Cells,” in Proceeding of IEEE International Symposium Circuit and Systems, pp. 224-608, Feb. 2008.
[14]Pyung-Su Han and Woo-Young Choi, “1.25/2.5-Gb/s Burst-Mode Clock Recovery Circuit with a Novel Dual Bit-Rate Structure in 0.8n-1m CMOS,” in Proceeding of IEEE International Symposium Circuit and Systems, pp. 3069-3072, 2006.
[15]Inhwa Jung, Daejung Shin, Taejin Kim and Chulwoo Kim, “A 140-Mb/s to 1.82-Gb/s Continuous-Rate Embedded Clock Receiver for Flat-Panel Displays,” in IEEE Transaction on Circuits and System II: Express Briefs, Vol. 56 , pp. 773-777, Oct. 2009.
[16]Moon-Sang Hwang, Sang-Yoon Lee, Jeong-Kyoum Kim, Suhwan Kim; Deog-Kyoon Jeong, “A 180-Mb/s to 3.2-Gb/s, Continuous-Rate, Fast-Locking CDR without Using External Reference Clock” in Proceeding of IEEE Asia Solid State Circuits Conference, pp. 144-147 , Nov. 2007.
[17]Rong-Jyi Yang, Kuan-Hua Chao and Shen-Iuan Liu, “A 200-Mbps 2-Gbps Continuous-Rate Clock-and-Data-Recovery Circuit,” in IEEE Transaction on Circuits and System I, Vol. 53, pp. 842-847, Apr. 2006.
[18]Shao-Hung Lin, Chang-Lin Hsieh and Shen-Iuan Liu, “A Half-Rate Bang-Bang Phase/Frequency Detector for Continuous-Rate CDR Circuits,” in Proceeding of IEEE Conference on Electron Devices and Solid-State Circuits, pp. 353–356, 2007.
[19]Ahmed, S.I., Kwasniewski and T.A., “OVERVIEW OF OVERSAMPLING CLOCK AND DATA RECOVERY CIRCUITS,” in Proceeding of IEEE Canadian Conference on Electrical and Computer Engineering, pp. 1876-1881, May. 2005.
[20]Robert Bogdan Staszewski, Chih-Ming Hung, Dirk Leipold, and Poras T. Balsara, “A first multigigahertz digitally controlled oscillator for wireless applications,” in IEEE Transactions on Microwave Theory and Techniques, Vol. 51, pp. 2154-2164, Nov. 2003.
[21]Tontisirin, S. and Tielert, R., “A Gb/s one-forth-rate CMOS CDR Circuit without External Reference Clock,” in Proceeding of IEEE International Symposium Circuit and Systems, pp. 3265-3268, 2006.
[22]Dalton, D., Chai, K., Evans, E., Ferriss, M., Hitchcox, D., Murray, P., Selvanayagam, S., Shepherd, P. and DeVito, L., “A 12.5-Mb/s to 2.7-Gb/s Continuous-Rate CDR With Automatic Frequency Acquisition and Data-Rate Readback,” in IEEE Journal of Solid-State Circuits, Vol. 40, pp. 2713-2725, Dec. 2005.
[23]Babulu. K. and Rajan. K.S., “FPGA IMPLEMENTATION OF USB TRANSCEIVER MACROCELL INTERFACE WITH USB2.0 SPECIFICATIONS,” in Proceeding of IEEE International Conference on Emerging Trends in Engineering and Technology, pp. 966-970, 2008.
[24]Hsuan-Jung Hsu, Chun-Chieh Tu, and Shi-Yu Huang, “A high-resolution all-digital phase-locked loop with its application to built-in speed grading for memory,” in Proceeding of IEEE Symposium on VLSI Design Automation and Test (VLSI-DAT), pp. 267-270, Apr. 2008.
[25]Ching-Che Chung and Wei-Cheng Dai; “An Referenceless All-Digital Fast Frequency Acquisition Full-Rate CDR Circuit for USB 2.0 in 65nm CMOS Technology,” i in Proceeding of IEEE International Symposium VLSI Design, Automation and Test (VLSI-DAT), pp. 1-4, 2011.
[26]Rong-Jyi Yang, Kuan-Hua Chao, Sy-Chyuan Hwu, Chuan-Kang Liang and Shen-Iuan Liu, “A 155.52 Mbps–3.125 Gbps Continuous-Rate Clock and Data Recovery Circuit,” in IEEE Journal of Solid-State Circuits, Vol. 41, pp. 1380-11390, Jun. 2006.
[27]Seon-Kyoo Lee, Young-Sang Kim, Hyunsoo Ha, Younghun Seo, Hong-June Park and Jae-Yoon Sim, “A 650Mb/s-to-8Gb/s Referenceless CDR Circuit with Automatic Acquisition of Data Rate,” in Proceeding of IEEE Solid-State Circuits Conference, pp. 184-185,185a, Feb. 2009.
[28]Chen-Yi Lee, and Ching-Che Chung, “Digital Loop Filter for All-Digital Phase-Locked Loop Design,” US patent 7,696,832 B1, Apr.13, 2010.
[29]Terng-Yin Hsu, Bai-Jue Shieh and Chen-Yi Lee, “An All-Digital Phase-Locked Loop (ADPLL)-Based Clock Recovery Circuit,” in IEEE Journal of Solid-State Circuits, Vol. 34, pp. 1063-1073, Aug. 1999.
[30]Hogge and C.R., Jr., “A Self Correcting Clock Recovery Circuit,” in IEEE Transaction on Electron Devices, Vol. 32, pp. 2704-2706, Dec. 1985.
[31]J. D. H. Alexander, “Clock recovery from random binary signals,” in IEEE Electronics Letters, Vol. 11, pp. 541-542, Oct. 1975.
[32]Kuo-Hsing Cheng, Cheng-Liang Hung and Chih-Hsien Chang, “A 0.77 ps RMS Jitter 6-GHz Spread-Spectrum Clock Generator Using a Compensated Phase-Rotating Technique,” in IEEE Journal of Solid-State Circuits, Vol. 46, pp. 1198-1213, May. 20011.