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研究生:謝宗翰
研究生(外文):Hsieh, Chung-Han
論文名稱:多通道長度次臨界電壓CMOS電路
論文名稱(外文):Multi-Channel-Length Sub-Threshold CMOS Circuits
指導教授:王進賢
指導教授(外文):Wang, Jinn-Shyan
口試委員:王進賢葉經緯楊博惠
口試委員(外文):Wang, Jinn-ShyanYeh, Ching-WeiYang, Po-Hui
口試日期:2011/07/26
學位類別:碩士
校院名稱:國立中正大學
系所名稱:電機工程研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2011
畢業學年度:99
語文別:中文
論文頁數:53
中文關鍵詞:多通道長度次臨界電壓反短通道效應
外文關鍵詞:Multi-Channel-LenghtSub-thresholdReverse short channel effect
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進入奈米製程時代,半導體元件透過製程步驟的調整,其特性隨之改變,如果始終維持舊有的設計方法,其電路效能與能源消耗將不會獲得良好的改善,反之,若是巧妙利用奈米製程帶來的副效應(反短通道效應)於電路設計中,將可提升電路效能。本論文利用台積電子65奈米製程來探討操作於次臨界電壓下之電路性能表現。
目前半導體晶圓廠在元件模組下並未特別提供專門給次臨界電壓電路設計使用,這使得次臨界電壓電路設計比起常壓操作電路設計要來的艱難,必須面對製程在次臨界電壓的漏電流情形。本論文將探討奈米製程臨界電壓對於次臨界電壓電路的影響,並利用反短通道效應設計標準元件庫以及正反器。最後利用台積電子65奈米製程測試ISCAS’2003 Benchmarks電路分析傳統式標準元件庫、全長通道式RSCE標準元件庫以及多通道長度設計概念在效能與功率損耗上的行為表現。

There are more special process procedure in nano era which changed the characteristic of semiconductor. The performance and energy consumption will get lost once designer still keep the same design technique without process consideration. A special byproduct called reverse short-channel-effect (RSCE) which can improve the circuit performance is involved. This paper will explore the circuit performance by utilizing TSMC 65 nm process.
At present, foundry didn’t provide the special model for sub-threshold circuit design application. It is difficult to design a sub-threshold circuit due to the leakage at the sub-threshold operation. This paper will focus on the nanometer technology circuit design at sub-threshold operation. And design the standard cell library and flip-flops with reverse short-channel-effect (RSCE). This paper is also describe a device size optimization which be considered for sub-threshold operation. Experiment results using ISCAS’2003 benchmarks and fabricated in TSMC 65nm CMOS technology show that the critical path delay, power consumption.

中文摘要
Abstract
表格目錄
附圖目錄
第一章 序論
1.1 研究動機
第二章 次臨界電壓電路設計分析
2.1 次臨界電壓電路設計概念
2.2 次臨界電壓下之元件特性
2.3 次臨界電壓之傳統電路設計
2.4 次臨界電壓之多通道長度電路設計
第三章 次臨界電壓之標準元件庫設計方法
3.1 傳統標準元件庫
3.1.1 模擬環境與條件
3.2 次臨界電壓之反短通道效應標準元件庫
3.2.1 模擬結果
第四章 次臨界電壓之正反器設計方法
4.1 傳統正反器電路
4.1.1 Setup time的定義
4.1.2 模擬環境與條件
4.2 改良式感測放大器型正反器 Improved Sense-Amplifier-Based Flip-Flop (ISAFF)
4.2.1 感測放大器型正反器 Sense-Amplifier Flip-Flop (SAFF)
4.2.2 改良式感測放大器型正反器Improved Sense-Amplifier-Based Flip-Flop (ISAFF)
4.2.3 設計準則
4.2.4 反短通道效應應用
4.2.5 模擬結果
4.3 條件擷取式正反器 Conditional-Capture Flip-Flop (CCFF)
4.3.1 動作原理
4.3.2 設計準則
4.3.3 反短通道效應應用
4.3.4 模擬結果
4.4 條件式最大時間借用正反器 Conditional Maximum Times Borrowing Flip-Flop (CMTBFF)
4.4.1 動作原理
4.4.2 設計準則
4.4.3 反短通道效應應用
4.4.4 模擬結果
4.5 比較三種正反器
第五章 模擬分析
第六章 結論與未來研究方向
6.1 結論
6.2 未來研究方向
第七章 參考文獻

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[2]The International Technology Roadmap for Semiconductors 2003, Tech. Rep. [Online]. Available: http://public.itrs.net/Files/2003ITRS/Home2003.htm.

[3]VLSI電路設計,王進賢,高立圖書。

[4]S. Mutoh, T. Douseki, Y. Matsuya, T. Aoki, S. Shigematsu, and J. Yamada, “1-V power supply high-speed digital circuit technology with multi threshold-voltage CMOS,” IEEE J. Solid-State Circuits, vol. 30, pp. 847–854, Aug. 1995.

[5]Sarvesh H Kulkarni, Ashish N Srivastava, and Dennis Sylvester, “A New Algorithm for Improved VDD Assignment in Low Power Dual VDD Systems,” in Proceedings of the 2004 International Symposium on Low Power Electronics and Design (ISLPED’04), pp. 200-205.

[6]L. Wei, Z. Chen, K. Roy, M. C. Johnson, Y. Ye, and V. K. De, “Design and Optimization of Dual-Threshold Circuits for Low-Voltage Low-Power Applications,” IEEE Trans. on Very Large Scale Integration (VLSI) Systems, vol. 7, no. 1, pp. 16-24, March 1999.

[7]Lee, D. Blaauw, and D. Sylvester, “Runtime leakage minimization through probability-aware dual-Vt or dual-tox assignment,” in Proceedings of the 2005 Asia and South Pacific Design Automation Conference, pp. 399-404.

[8]Tae-Hyoung Kim, John Keane, Hanyong Eom, and Chris H. Kim, “Utilizing Reverse Short-Channel Effect for Optimal Subthreshold Circuit Design,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 15, no. 7, pp. 821-829, July 2007.

[9]Stojanovic, V. ; Oklobdzija, V.G. ; Bajwa, R., “A unified approach in the analysis of latches and flip-flops for low-power systems ”, Low Power Electronics and Design, pp.227-232, 1988.

[10]Stojanovic, V.; Oklobdzija, V.G., “Comparative analysis of master-slave latches and flip-flops for high-performance and low-power systems”, IEEE J. Solid-State Circuits, pp. 536-578, 1999.

[11]Matsui, M. ; Hara, H. ; Uetani, Y. ; Lee-Sup Kim ; Nagamatsu, T. ; Watanabe, Y. ;Chiba, A. ; Matsuda, K. ; Sakurai, T. , “A 200 MHz 13 mm2 2-D DCT macrocell using sense-amplifying pipeline flip-flop scheme” , IEEE International Solid-State Circuits Conference, pp. 1482-1490 , 1994.

[12]Nikolic, B. ; Oklobdzija, V.G. ; Stojanovic, V. ; Wenyan Jia ; James Kar-Shing Chiu ;Ming-Tak Leung, M. , “Improved sense-amplifier-based flip-flop: design and measurements” , IEEE J. Solid-State Circuits, 2000, 35, pp. 876-884.

[13]Bai-Sun Kong ; Sam-Soo Kim ; Young-Hyun Jun , “Conditional-capture flip-flop for statistical power reduction” , IEEE J. Solid-State Circuits, 2001, 36, pp. 1263-1271

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