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研究生:張介豪
研究生(外文):Chang, Chiehhaw
論文名稱:多天線系統下K-Best檢測器硬體架構設計與實現
論文名稱(外文):Hardware Architecture Design and Realization of the K-Best Detector for MIMO Communication Systems
指導教授:劉宗憲劉宗憲引用關係
指導教授(外文):Lui, Tsunghsien
口試委員:劉宗憲蔡佩芸邱茂清陳喬恩胡家璋
口試委員(外文):Lui, TsunghsienTsai,PeiyunChiu, MaochingChen, ChiaoenHu, Chiachang
口試日期:2011-07-06
學位類別:碩士
校院名稱:國立中正大學
系所名稱:通訊工程研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2011
畢業學年度:99
語文別:中文
論文頁數:42
中文關鍵詞:多天線K-Best樹狀搜尋電路合成
外文關鍵詞:MIMOK-Besttree searchsynthesis
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在多天線(MIMO) 系統下, 一般認為最好的檢測器(detector) 是最大相似度檢測(maximumlikelihood detector, MLD) , 但是MLD 的複雜度過高也是大家所熟知的問題, 因此有許多降低MLD 複雜度的演算法因應而生。K-Best 檢測器則是對MLD 做簡化, 一樣是在做樹狀搜尋(tree search) , 在每一個階層展開後只留下K 個最小PED(partial Euclidean distance) 的節點, 再由這K 個節點繼續下一階層的展開。此方法能夠大量的降低複雜度, 但是並沒有搜尋到所有的晶格點(latticepoint) , 有可能將正確的答案捨棄掉, 所以K-Best 檢測器只能算是次佳的檢測器。在這個K-Best 硬體架構中, 我設定的環境是在4×4的實數多天線系統, 使用的是16QAM 調變, K值設定為4 , 在硬體參數中全部都以18位元代表一個數值的值,而在傳送符元(symbol)方面則是以2位元代表。那硬體架構是使用管線化(pipeline)的方法, 如此來加速整體的產出率(throughput) , 但也會因此犧牲掉一些面積。在電路設計部分使用Xilinx ISE 進行Verilog 程式撰寫再以matlab 為輔助驗證的方式測試程式功能的正確性, 並且使用xc4vlx100-12ff1148這塊板子進行電路合成(synthesis), 最後合成結果最大操作頻率為191.6MHz , 產出率為161.4Mbps 。
In the multiple-input multiple-output (MIMO) systems, the maximum likelihood detector (MLD) is the optimal detector. But, the MLD requires very high computational complexity; therefore, many suboptimal detectors are developed. The suboptimal K-Best detector is a low-complexity tree search detector that performs closely to the MLD. At each level of the tree, only K nodes with the smallest partial Euclidean distance (PED) are retained. The K-Best detector is especially suitable for hardware implementation, because of its possible parallel architecture. We design the real-valued K-Best hardware architecture for detecting 16-QAM signals in the 4-by-4 MIMO system. The parameter K is selected to be 4. Every 18 bits are used to represent a real number. Every 4 bits are used to represent a 16-QAM signal. A pipelined architecture is adopted to improve the throughput rate, but it may increase the designed chip area. The designed hardware is described by Verilog codes, function verified by Xilinx ISE, and synthesized according to the xc4vlx100-12ff1148 FPGA board. The synthesis results reveal that our designed K-Best architecture can work with maximum frequency 191.6 MHz and work at throughput rate 161.4 Mbps.


1 導論1
1.1 前言. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 研究動機. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.3 內容大綱. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2 多天線通訊系統3
2.1 多天線通訊系統簡介. . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.2 多天線系統模型. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.3 MIMO檢測器. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3.1 Zero-forcing linear detection . . . . . . . . . . . . . . . . . . . 8
2.3.2 MMSE linear detection . . . . . . . . . . . . . . . . . . . . . . 10
2.3.3 最大相似度檢測器. . . . . . . . . . . . . . . . . . . . . . . . 11
3 K-Best演算法12
3.1 傳統K-Best 演算法. . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.2 改善方法. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.2.1 SE列舉法. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.2.2 預處理排序. . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4 K-Best硬體架構設計22
4.1 架構設計前言. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.2 K-Best硬體架構. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.3 硬體架構的參數調整. . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5 模擬結果與效能比較32
5.1 K-Best架構時序模擬結果. . . . . . . . . . . . . . . . . . . . . . . . . 32
5.2 電路合成結果與比較. . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6 結論與未來工作39
參考文獻40

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