臺灣博碩士論文加值系統

科技的進步，電子產品都往輕、薄、短、小的方向發展，然而礙於物理極限的關係，已經陷入瓶頸。為了尋求高功率、高密度低成本的製程，所以採用三維堆疊式晶片的方式進行。
本研究主要目的是針對特定 3D 堆疊封裝結構進行應力分析，主要是要探討對於 3D 堆疊式晶片各種添加底膠的方式，對於整個構裝體的影響。分析方法採用有限元素軟體 ANSYS，以四分之ㄧ對稱之全域模型進行 TCT 熱循環測試模擬，採用JESD22-A104-B 規範條件，以了解各層元件的應力與應變分布，考慮 SnAg 低鉛錫球為黏塑性或潛變-塑性，探討錫球壽命可靠度。同時利用次結構技巧，針對應力或應變較大之關鍵位置，進行局部區域分析。完成基準模型分析之後，對於各種添加底膠方式不同的模型進行比較，進而瞭解何種填膠的方式對於構裝體的保護是比較好的。
根據模擬分析之後的結果，可以發現不同底膠的添加形式對於 3D 堆疊封裝結構會有不同的影響，對於銲錫凸塊周圍進行填膠與否的模型，可以發現對於銲錫凸塊的保護是有直接的影響，而對於銲錫微凸塊周圍進行填膠與否的模型，發現對於銲錫凸塊的保護沒有很直接的影響，對於 TSV 而言，銲錫微凸塊進行填膠不一定會比較好，但只是些微的不好，數值上差異不大，觀察 interposer 的時候也可以發現整體數值變異不大，而對於晶片而言，各層晶片的應力狀況，可以發現在第一層晶片的應力值是比較小的，不同於其他層晶片應力值，因為在最上層沒有其他束制，可以自由的彎曲使得應力可以釋放掉，而其他層的應力狀況都很接近，因為上下束制住無法讓應力釋放掉，單純對於整個構裝體進行考慮的話，銲錫凸塊周圍進行填膠以及銲錫微凸塊進行填膠，是對於整體有比較好的保護。

Solder joint reliability plays a great concern to semiconductor and electronic product manufacturers. In the past years, thermal cycling test to solder joints fatigue strength has been investigated vigorously. To pursue further performance improvement of semiconductor devices in the next decades, three-dimensional (3D) chip integration with through silicon Via (via) would be one of the key technologies. Although 3D packaging technologies are progressively investigated and applied to enhance better performance of IC packages, thermal-mechanical loading and its effect on reliability needs to be studied for optimum the overall packages.
This study focuses on the finite element simulation to predict the effect of umderfill to the bump joints fatigue life and stress and strain distribution in each component of a specified 3D stacked packages . The comparison of finite element models includes with undefill in bump and microbump, without undefill in bump and microbump, with undefill in bump and with underfill in microbump, and without undefill in bump and with underfill in microbump.
The 3D package consists of four vertical dies with micro bump, Si interposer with TSV and bump beneath, organic substrate. A fourth symmetric model is generated using ANSYS as a finite element solver. The loading condition is simulated under accelerated temperature cycle in ranging of 0 °C to 100 °C. The bump life and micro bumps stress and strain is investigated by submodel technology.
This study observed that (1) micro bump with underfill reduces the DNP corner wrapage and bump with underfill does not provide a better DNP corner wrapage; (2) bump with underfill greatly reduces the bump stress and strain and minor that of effect for microbump with underfill; (3) micorbump with underfill presents a better stress performance but reverse for bump with underfill; (4) there is no significant effect for interposer, chip and TSV whether underfill exist or not; (5) better bump life is protected by underfill but microbump with underfill do not have contribution to the bump life.

摘要 i
ABSTRACT ii
致謝 iv
目錄 v
表目錄 vii
圖目錄 viii
第一章 緒論 1
1-1 前言 1
1-2 文獻回顧 4
1-3 研究動機 6
1-4 研究方法 7
1-4-1數值模擬簡介 7
1-4-2模型填膠方式設計 9
第二章 有限元素模型 11
2-1 構裝體幾何尺寸及材料性質 14
2-2 全域模型 16
2-3 次模型 17
2-4 邊界條件與負載設定 19
2-5 塑性與潛變分析模型 21
2-6 疲勞壽命預測 22
第三章 結果與討論 24
3-1 不同填膠方式比較 24
3-2 模型填膠方式選定 27
3-3 三維堆疊式晶片有無添加底膠之比對 29
3-4 次模型與預測疲勞壽命 48
第四章 結論 56
參考文獻 58

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