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研究生:謝明周
研究生(外文):Ming-Jhou Sie
論文名稱:四位元快閃式類比/數位轉換器
論文名稱(外文):4-Bit flash analog-to-digital converter
指導教授:呂輝宗林坤緯林坤緯引用關係
學位類別:碩士
校院名稱:建國科技大學
系所名稱:電子工程系暨研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2011
畢業學年度:99
語文別:中文
論文頁數:75
中文關鍵詞:Positive FeedbackHysteresisThermometer CodeBinary Code
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我們以TSMC0.35μm2P 4M製程技術設計一個正回授(Positive Feedback)比較器的3-bit 20MS/s快閃式類比數位轉換器和遲滯(Hysteresis)比較器的4-bit 1GS/s快閃式類比數位轉換器。
電路結構利用電阻陣列產生了參考電位,再將其參考電位輸入比較器中與輸入的電位比較,而所得到溫度計碼(Thermometer Code)的值經由前置編碼電路(1-out-of-N)與後置編碼電路(Binary Code)編碼後輸出。
本論文的4-bit快閃式類比數位轉換器,其工作電壓區間為0.9至2.2伏特,取樣率為1GHz,消耗功率為5.158 mW之四位元快閃式類比數位轉換器,整體電路佈局面積為(含PAD) 1.445×1.393mm 。而3-bit快閃式類比數位轉換器,其工作電壓區間為0至3.3伏特,取樣率為20MHz,消耗功率為2.2228mW之三位元快閃式類比數位轉換器,整體電路佈局面積為(含PAD) 1.181×1.326mm 。

We use TSMC0.35μm2P 4M technology to design a positive feedback 3-bit 20MHz flash analog-to-digital converter and a 4-bit 1GHz flash analog-to-digital converter with hysteresis comparator.
Reference potential was generated by resistor array, then compared with the input potential, and the resulting thermometer code pass through the pre-encoding circuit (1-out-of-N) and post-encoding circuit (Binary Code) after output.
The 4-bit flash analog-to-digital-converter features working voltage range from 0.9 to 2.2 V, sampling rate of 1GHz, the power consumption is 5.158 mW and the chip layout area is 1.445×1.393mm . For 3-bit flash analog-to-digital converter, the working voltage ranges from 0 to 3.3 V, sampling rate of 20MHz, the power consumption is 2.2228mW and the chip layout area is 1.181 × 1.326 mm .

目錄
中文摘要....................................................................................................I
英文摘要..................................................................................................II
誌謝..........................................................................................................III
目錄...........................................................................................................Ⅴ
圖目錄.......................................................................................................Ⅷ
表目錄……………………………………………………………………………...XI
第一章 緒論...............................................................................................1
壹、研究動機......................................................................................4
貳、設計流程......................................................................................7
參、電路整體動作..............................................................................8
肆、論文架構......................................................................................9
第二章 類比數位轉換器之基本概念....................................................11
壹、介紹............................................................................................11
貳、類比數位轉換器的簡介...........................................................12
參、類比數位轉換器的功能與用途...............................................15
肆、類比數位轉換器的架構...........................................................21
一、摺疊式類比數位轉換器(Folding ADC)...........................21
二、兩階段式類比數位轉換器(Two Step ADC).....................24
三、管線式類比數位轉換器(Pipeline ADC)..........................25
四、快閃式類比數位轉換器(Flash ADC)...............................28
五、3位元之比較器架構..........................................................32
六、4位元之比較器架構..........................................................34
第三章 快閃式類比數位轉換器(Flash A/D)之泡沫編碼...............37
壹、介紹............................................................................................37
貳、避免泡沫雜訊............................................................................38
參、造成泡沫錯誤原因...................................................................40
一、泡沫錯誤的更正.................................................................41
肆、傳統二進制ROM-Based的編碼器........................................44
一、電路功能.............................................................................44
二、編碼系統.............................................................................47
伍、Gray ROM-Based的編碼器...................................................48
一、電路功能.............................................................................49
二、編碼系統.............................................................................51
第四章 電路實體佈局模擬結果與三位元晶片結果及討論................53
壹、三位元類比數位轉換器佈局模擬結果...................................53
貳、四位元類比數位轉換器佈局模擬結果...................................57
參、晶片測試結果............................................................................61
VI
一、預計規格與實測結果.........................................................61
二、測試方法及儀器.................................................................61
三、測試結果.............................................................................65
肆、本論文轉換器與其他轉換器之比較.......................................67
一、三位元.................................................................................67
二、四位元.................................................................................68
第五章 結論及未來的研究方向....................................................69
壹、結論............................................................................................69
貳、未來的研究方向........................................................................70
參考文獻..................................................................................................71
附錄...........................................................................................................74
作者簡介..................................................................................................75
圖目錄
頁次
圖1-1 快閃式類比數位轉換器設計流程................................................7
圖1-2 快閃式類比數位轉換器的結構電路內部結構............................8
圖2-1 類比數位轉換器方塊圖..............................................................12
圖2-2 OPAmp數量成長示意圖.............................................................17
圖2-3 微分非線性誤差示意圖...............................................................19
圖2-4 積分非線性誤差示意圖...............................................................21
圖2-5 摺疊式類比數位轉換器架構圖..................................................23
圖2-6 兩階段式類比數位轉換器架構圖..............................................25
圖2-7 管線式類比數位轉換器架構圖..................................................27
圖2-8 快閃式類比數位轉換器架構圖..................................................31
圖2-9 正回授比較器示意圖..................................................................32
圖2-10 突波回授雜訊示意圖.................................................................33
圖2-11 Class-AB比較器架構.................................................................34
圖2-12 比較器之遲滯曲線....................................................................35
圖2-13 遲滯比較器架構........................................................................36
圖3-1 泡沫錯誤示意圖..........................................................................37
圖3-2使用NAND避免泡沫雜訊...........................................................39
VIII
圖3-3 抓取特徵字串邏輯圖..................................................................42
圖3-4 投票電路邏輯圖..........................................................................43
圖3-5 投票電路與真值表......................................................................43
圖3-6 4-bit二進制ROM-Based的溫度計碼到二進制編碼器.............45
圖3-7 1-out-of-N電路轉換器.................................................................46
圖3-8 3位元傳統二進制ROM-Based的編碼系統..............................47
圖3-9 3位元傳統二進制ROM-Based的編碼系統發生泡沫錯誤......48
圖3-10 4-bit Gray ROM-Based的溫度計碼到二進制編碼器............50
圖3-11 3位元Gray ROM-Based的編碼系統.......................................51
圖3-12 3位元Gray ROM-Based的編碼系統發生泡沫錯誤..............52
圖4-1 溫度計碼模擬圖..........................................................................53
圖4-2 編碼模擬圖(1-out-of-N).............................................................54
圖4-3 3位元輸出模擬圖........................................................................55
圖4-4 3位元快閃式類比數位轉換器之電路佈局圖............................56
圖4-5 3位元快閃式類比數位轉換器之電路佈局圖(含PAD).............57
圖4-6 溫度計碼模擬圖..........................................................................58
圖4-7 編碼模擬圖(1-out-of-N).............................................................58
圖4-8 4位元輸出模擬圖........................................................................59
圖4-9 4位元快閃式類比數位轉換器之電路佈局圖............................60
IX
圖4-10 4位元快閃式類比數位轉換器之電路佈局圖(含PAD)...........60
圖4-11 測試方法示意圖........................................................................62
圖4-12 參考電壓示意圖........................................................................62
圖4-13 取樣率示意圖............................................................................63
圖4-14 輸入電壓示意圖........................................................................64
圖4-15 輸出碼示意圖............................................................................64
圖4-16 輸出碼示意圖............................................................................65
圖4-17 PAD腳位示意圖.........................................................................66
圖4-18 輸出電壓示意圖........................................................................66
X
表目錄
頁次
表2-1 奈奎氏類比數位轉換器的特性比較...........................................14
表3-1 Thermometer code、Binary code及Decimal對照表................39
表3-2 Thermometer code、Gray code、Binary code及Decimal對照表.....49
表4-1 規格表..........................................................................................61
表4-2 三位元論文結果比較表..............................................................67
表4-3 四位元論文結果比較表..............................................................68
[1] Krishnaswamy Nagaraj,David A. Martin, Mark Wolfe, Ranjan
Chattopadhyay, Shanthi Pavan, Jason Cancio, T. R. Viswanathan, “A Dual-Mode 700-Msamples/s 6-bit 200-Msamples/s 7-bit A/D
Converter in a 0.25-μm Digital CMOS Process”,IEEE Journal of
Solid-State Circuits, Vol.35 No.12, pp. 1760-1768, Dec. 2000.
[2] Neil H.E. Weste, Karman Eshraghian, Principles of CMOS VLSI
Design 2nd ed.,Addison Wesley. pp. 694-702 , 1994.
[3] KeiiChi Kusumoto and Akira Matsuzawa, “A 10-b 20-MHz 30 mW
Pipelined Interpolating CMOS ADC”, IEEE Journal of Solid-State
Circuit, Dec. 1993.
[4] Walter Ciciora, Gary Sgrignoli, and William Thomas, “A tutorial on
ghost can-celling in television system“, IEEE Transactions on Consumer Electronics, vol. CE-25, pp. 9-44, Feb.1979.
[5] Phillip E. Allen and Douglas R. Holberg “CMOS Analog Circuit
Design”, Oxford, 1987.
[6] R.V.D. Plassche, Integrated Analog-to-Digital an Digital-to-Analog
Converters, Kluwer Academic Publishers,Chap.4,1994.
[7] U. Tietze and C. Schenk, Electronic Circuits Chapter23 ,
Springer-Verlag Berlin Heidelberg,1992.
[8] David A. Johns and Ken Martin, ”Analog Integrated Circuit Design,”
John Wiley & Sons, Inc., 1997.
[9] 唐正哲,管線式類比數位轉換器設計,碩士論文,國立暨南國際大學電機工程學系,2008。
71
[10] Behzad Razavi, Principle of Data Conversion System Design, John
Wiley and Sons Publishers, 1995.
[11] 余紳豪,低電壓雙重取樣管線式類比數位轉換器之研究,碩士論文,國立雲林科技大學電子工程系,2005。
[12] P. Amaral, J. Goes, Paulino, and A. Steiger-Garcao, “An Improved
Low-Voltage Low-Power CMOS Comparator to be used in High-Speed Pipeline ADCs”, Proceedings of the 2002 IEEE International Symposium on Circuits and Systems Vol.5, Page. V141-V144, 2002.
[13] Phillip E. Allen and Douglas R. Holberg, CMOS Analog Circuit
Design, Oxford, New York, 1987.
[14] Neil H.E. Weste, Karman Eshraghian, Principles of CMOS VLSI
Design 2nd ed.,Addison Wesley. pp. 694-702,1994.
[15] A. Yukawa, “A CMOS 8-Bit High-Speed A/D Converter IC”, IEEE
Journal of Solid-State Circuit, Vol. 20, No. 3, Jun. 1985, pp. 775-779.
[16] 林凱琪,高速快閃式類比數位轉換器,碩士論文,國立台北科
技大學電腦通訊與控制研究所,2002.
[17] Sanroku Tsukamoto, William G. Schofield, Toshiaki Endo, “A
CMOS 6-b,400-MSample/s ADC with Error Correction”, IEEE
journal of Solid-State Circuit , Vol. 31, No. 11, pp. 1931-1836, Dec. 1996.
[18] B. Razavi, Principle of Data Conversion System Design. New York:
Wiley 1995.
72
[19] 謝傑宇、蔡志墝,四位元快閃式類比對數位轉換器,專題製作,國立雲林科技大學電子工程系,2004
[20] 莊堯仁,採用新式泡沫容忍編碼器之1GHz六位元,碩士論文,國立成功大學電機工程系,2005
[21] 呂輝宗、蔡佩娟、謝明周,一個具有20MHz快閃式類比/數位轉換器,2009系統雛型與電路設計創新應用研討會論文集,P115,2009
[22] Subhadeep Banik, Daibashish Gangopadhyay and T. K. Bhattacharyya, “A low power 1.8V 4-bit 400-MHz flash ADC in .18μm Digital CMOS”, Proc. of IEEE VLSID, 2006.
[23] Sanjay G. Talekar and S. Ramasamy “A Low Power 700MSPS 4bit Time Interleaved SAR ADC in 0.18um CMOS”, National Institute of Technology Tiruchirappalli,2009
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