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研究生:黃嘉弘
研究生(外文):Jia-Hong Huang
論文名稱:雙延遲路徑環形壓控振盪器之設計與分析
論文名稱(外文):Design and Analysis of Voltage Controlled Ring Oscillator with Dual Delay Paths
指導教授:陳淳杰
指導教授(外文):Chun-Chieh Chen
學位類別:碩士
校院名稱:中原大學
系所名稱:電子工程研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2011
畢業學年度:99
語文別:中文
論文頁數:54
中文關鍵詞:環型壓控震盪器雙延遲路徑
外文關鍵詞:Voltage-Controlled Ring OscillatorDual delay paths
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在現今這個科技迅速發展的時代,通訊系統的進步也是以驚人的速度進行。而在通訊系統中的訊號接收與發射端需要一精確且穩定的振盪訊號來和欲發射的訊號以及接收的訊號進行混波,因此產生本地震盪訊號的壓控振盪器即扮演著十分重要的角色。 本篇論文針對一個同時結合對稱負載(Symmetric Load)、負時滯電路(Negative Skewed Delay)及PMOS構成的交叉耦合對(Cross-Coupled Pair)所設計的雙迴路環形壓控振盪器(Voltage Controlled Ring Oscillator with Dual Delay Paths)進行整理及分析。電路架構由三級差動放大對所構成,藉由使用對稱負載做為可變負載增加電路的線性度將可降低來自電源供應端的雜訊,加入負時滯電路架構也將加速振盪器的振盪速度,同時在設計與分析的章節中利用震盪頻率的公式推導進行驗證。本環形壓控振盪器以台灣積體電路公司(TSMC)之1P6M 0.18μm RF-CMOS製程去實現,共使用33顆RF-CMOS電晶體,其中24顆為RF-PMOS而其餘9顆為RF-NMOS。量測結果之頻率調整範圍由2.77GHz到4.55GHz,其中頻率調整百分比為49%。同時相位雜訊在中心頻率2.77GHz之1MHz偏移處為-92dBc/Hz;在中心頻率4.55GHz之1MHz偏移處為-96dBc/Hz。

Nowadays, the communication system was a rapidly developed technology. At the architecture of transceiver and receiver, we need a precise and stable oscillated signal to mix with the radio frequency signal. Thus, the voltage controlled ring oscillator used to produce the local oscillated signal played an important role. This paper presented an analysis on a voltage controlled ring oscillator with dual delay paths with symmetric load、negative skewed delay and PMOS cross coupled pair. The circuit was a three-stage differential ring oscillator, with symmetric load as a variable resistor to improve the linearity of circuit will reduce the noise from power supply. This circuit using negative skewed delay to accelerated the oscillation frequency, at the chapter of analysis will prove it with the equation of oscillation frequency. The VCRO was implemented using a TSMC 0.18 μm RF-CMOS process. All devices in this circuit was 33 RF-MOS transistor, 24 of them were RF-PMOS and rest of them were RF-NOMS. Measurement results demonstrate that the VCRO achieves a frequency tuning range of 2.77 GHZ to 4.55 GHz, the frequency tuning percentage was 49%. The measured phase noise at 1 MHz offset from the carrier frequency 4.55 GHz is -96 dBc/Hz. The VCRO occupies an active area of 0.048 mm2 and consumes 50.76mW for 4.55 GHz carrier frequency from a 1.8 V power supply.

目錄
摘要...............................................................................................................................I
Abstract........................................................................................................................II
致謝..............................................................................................................................III
目錄...............................................................................................................................V
圖目錄........................................................................................................................VII
表目錄..........................................................................................................................IX
第一章 緒論............................................................................................................1
1.1研究背景..........................................................................................................1
1.2研究動機..........................................................................................................1
1.3研究方法..........................................................................................................2
1.4論文架構..........................................................................................................3
第二章 壓控振盪器架構與考量............................................................................4
2.1簡介..................................................................................................................4
2.2振盪器基本原理..............................................................................................4
2.2.1LC-tank 壓控振盪器 [2]..............................................................................5
2.2.2環形壓控振盪器...................................................................................8
2.3環形振盪器之雜訊考量................................................................................11
2.3.1雜訊介紹.............................................................................................12
2.3.2熱雜訊(Thermal noise) [2].................................................................12
2.3.3閃爍雜訊(Flicker Noise) [2]...............................................................14
2.3.4散射雜訊(Shot Noise) [2]...................................................................15
2.3.5 MOS 雜訊模型..................................................................................15
2.3.6環形壓控振盪器之相位雜訊 [2][3].................................................16
第三章 雙延遲路徑環形壓控振盪器之設計與分析..........................................24
3.1簡介................................................................................................................24
3.2雙延遲路徑環形壓控振盪器之架構............................................................24
3.2.1對稱負載.............................................................................................24
3.2.2負時滯電路.........................................................................................26
3.3壓控振盪器之電路設計................................................................................31
3.3.1壓控振盪器之電路與設計流程.........................................................31
3.3.2壓控振盪器之振盪頻率分析.............................................................33
3.3.2壓控振盪器小訊號參數分析.............................................................36
3.4模擬與量測結果............................................................................................37
第四章 結論與展望..............................................................................................42
V
參考文獻......................................................................................................................43

圖目錄
圖 1-1直接降頻收發機架構.......................................................................................2
圖 2-1回授系統...........................................................................................................4
圖 2-2不同相位偏移之回授系統...............................................................................5
圖 2-3 (a)實際LC並聯電路(b)實際LC串聯電路........................................................6
圖 2-4單埠振盪器電路示意圖...................................................................................6
圖 2-5 (a)交叉耦合對電路(b) 交叉耦合對小訊號等效電路....................................7
圖 2-6 NMOS 交叉耦合對型態之LC壓控振盪器....................................................8
圖 2-7 在時域中分析環形振盪器震盪頻率之示意圖..............................................9
圖 2-8 在頻域中分析環形振盪器之震盪頻率..........................................................9
圖 2-9 箝制示意圖....................................................................................................10
圖 2-10 環形壓控振盪器之頻率調整(a)控制負載電容(b)控制負載電阻(c)控制驅動能力..........................................................................................................11
圖 2-11 電阻雜訊模型..............................................................................................13
圖 2-12 MOSFET之熱雜訊模型...............................................................................14
圖 2-13 MOS雜訊等效模型.......................................................................................16
圖 2-14 (a)理想振盪器輸出頻譜(b)實際振盪器輸出頻譜......................................17
圖 2-15 相位雜訊在無線通訊系統所造成之鄰近通道干擾..................................18
圖 2-16 相位雜訊在發射端所造成之影響..............................................................19
圖 2-17 Leeson’s 相位雜訊模型...............................................................................20
圖 2-18 CMOS反相器串接環形振盪器....................................................................21
圖 2-19 在不同時間對波形造成之影響(a) 當脈衝出現在擺幅上時(b) 當脈衝出現在轉態點附近時......................................................................................22
圖 2-20 環形振盪器之(a)波形與(b)脈衝敏感方程式(ISF,impulse sensitivity function).......................................................................................................23
圖 3-1 (a) 對稱負載電路結構 (b) 對稱負載之I-V曲線.........................................25
圖 3-2 使用ADS模擬對稱負載在不同控制電壓下之I-V曲線...............................26
圖 3-3 (a)傳統單級電路 (b)負時滯架構之單級電路..............................................27
圖 3-4 負時滯結構跟傳統結構之暫態波型的時序比較圖....................................28
圖 3-5 負時滯電路架構中輸入訊號之示意圖........................................................29
圖 3-6 反相器構成之環形振盪器(a)傳統反相器構成之環形振盪器(b)負時滯電路架構之環形振盪器示意圖(c)負時滯電路架構之環形振盪器實現圖.30
圖3-7 傳統環形振盪器與負時滯電路架構振盪器之輸出波形.............................30
圖3-8 (a)環形壓控振盪器電路 (b)環形壓控振盪器單級電路...............................32
圖3-9 環形壓控振盪器之設計流程.........................................................................33
圖3-10 環形壓控振盪器之小訊號等效模型...........................................................34
VII
圖3-11環形壓控振盪器單級電路之小訊號等效模型............................................37
圖 3-12 雙迴路之環形壓控振盪器的(a)晶片照相圖以及(b)佈局圖.....................38
圖 3-13(a) 輸出頻率在 4.55GHz之頻譜(b) 輸出頻率在 2.77GHz之頻譜........39
圖 3-14(a)中心頻率為4.55 GHz之相位雜訊 (b) 中心頻率為2.77 GHz之相位雜訊..................................................................................................................40
圖 3-15雙迴路環形壓控振盪器之頻率調整範圍...................................................41

表目錄
表 3.1 環形壓控振盪器單級電路中各個電晶體長寬比.........................................38
表 3.2 與其他環形壓控振盪器之比較.....................................................................41
參考文獻
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[4] Tuan Vu Cao, Dag T. Wisland, Tor Sverre Lande, and Farshad Moradi, “Low Phase-Noise and Wide Tuning-Range CMOS Differential VCO for Frequency ΔΣ Modulator,” IEEE Computer Society Annual Symposium, 2009, pp. 13-18.
[5] Merrick Brownlee, Pavan Kumar Hanumolu, Un-Ku Moon and Karti Mayaram, “ The Effect Of Power Supply Noise On Ring Oscillator Phase Noise,” 2nd Annual IEEE Northeast Workshop on Circuits and Systems,2004,pp. 225-228.
[6] Luciano Severino de Paula, Sergio Bampi, Eric Fabris and Altamiro Amadeu Susin, “A High Swing Low Power CMOS Differential Voltage-Controlled Ring Oscillator,” 14th IEEE International Conference on Electronics,Circuits and Systems,2007,pp. 498-501.
[7] J. G. Maneatis and M. A. Horowitz, “Precise delay generation using coupled oscillators,” IEEE Journal Solid-State Circuits, vol. 28, pp.
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1273–1282,Dec. 1993.
[8] Ge Yan, Chen Zhongjian, Fen Wennan and Ji Lijiu, ” Design of CMOS High Speed Self-Regulating VCO Using Negative Skewed Delay Scheme,” IEEE7th International Conference on Solid-State and Integrated Circuits Technology,2004,pp. 1333-1336.
[9] Seog-Tun Lee, Beomsup Kim and Kwyro Lee, “A Novel High-Speed Ring Oscillator for MuItiphase Clock Generation Using Negative Skewed DelayScheme,” IEEE JournaI of Solid-State Circuit, Vol.32, No. 2, Feb.1997.
[10] L. Sun, T. Kwasniewski, and K. Iniewski, “A quadrature output voltagecontrolledring oscillator based on three-stage subfeedback loops,” IEEE International Symposium Circuits and Systems (ISCAS), vol. 2, 1999, pp. 176–179.
[11] L. Sun and T. A. Kwasniewski, “A 1.25-GHz 0.35-μm monolithicCMOS PLL based on a multiphase ring oscillator,” IEEE Journal Solid-State Circuits, vol. 36, no. 6, pp. 910–916, Jun. 2001.
[12] Hai Qi Liu, Wang Ling Goh, Liter Siek, Wei Meng Lim and Yue Ping Zhang,” A Low-Noise Multi-GHz CMOS Multiloop Ring Oscillator With Coarse and Fine Frequency Tuning,” IEEE Transactions on Very Large Scale Integration Systems (VLSI), vol. 17, no. 4, April.2009.
[13] Ping Lu, Danfeng Chen, Fan Ye and Junyan Ren, “A 5.4GHz wide tuning range CMOS PLL using an auto-calibration multiple-pass ring oscillator,” IEEE SOC Conference, 2009, pp. 39-42.
[14] Tianwang Li, Bo Ye and Jinguang Jiang, “0.5 V 1.3 GHz voltage controlled ring oscillator,” Conference on ASIC, 2009, pp. 1181-1184.
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[15] Jihai Duan, Zhilan He, Chunlei Kang, Jianfeng Wang and Jizuo Zhang,” A Multiloop Ring VCO Design in 0.18μm CMOS Technology” IEEE International Conference on Solid-State and Integrated Circuit Technology, 2010, pp.99-101.
[16] 倪志瑋,” 使用0.18-μm CMOS 製程之多重路徑低功耗6.44-GHz 之壓控振盪器設計”元智大學通訊工程研究所碩士論文,2010
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