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研究生:范匡利
研究生(外文):Kuang-Li Fan
論文名稱:功率半導體元件設計與製程開發
論文名稱(外文):Structure Design and Process Development of Power Field Effect Transistors
指導教授:魏拯華
學位類別:碩士
校院名稱:清雲科技大學
系所名稱:電子工程所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2011
畢業學年度:99
語文別:中文
論文頁數:61
中文關鍵詞:液相沉積法氧化層超接面技術
外文關鍵詞:LPDoxideSuper Junction.
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本論文第一部分研究以利用液相沉積法加退火製程成長良好的絕緣層在氮化鎵上,實驗先使用液相沉積法在低溫(<50℃)將二氧化矽沉積在氮化鎵/藍寶石基板上,將金屬電極以金/鈦或金/鉻為材料,蒸鍍在二氧化矽層上,接著退火400℃到900℃,藉金屬電極外加偏壓來作氧化層之漏電流量測分析比較。
第二部分研究超接面金氧半功率場效電晶體之電性模擬,了解具有高摻雜濃度的超級接面結構能夠有效改善崩潰電壓與導通電阻之間的關係。使用半導體元件模擬軟體為ISE TCAD,首先利用設計之元件結構來找出pn柱狀結構之最佳摻雜濃度、p型柱狀溝槽之最佳深度。再分析新設計元件結構對於崩潰電壓與導通電阻的影響。

In the first part of this paper, we try to grow a quality insulating film on the surface of GaN by the liquid phase deposition (LPD) and post annealing. After collecting and analyzing the leakage current of the insulator, we will find a suitable thickness of insulator and the annealing procedure.
Secondary, we also study the high voltage semiconductor device – super junction metal oxide semiconductor field effect transistor (SJ MOSFET) by the simulation tools. In this thesis, a new structure of MOSFET is proposed. After the TCAD simulation, the on-resistance, breakdown voltage of the devices are collected under different geometry and doping concentration. From above data, we can find a good recipe and process window for the SJ MOSFET.

中文摘要………………………………………………………………… i
英文摘要……………………………………………………………… ii
誌謝…………………………………………………………………… iii
目錄…………………………………………………………………… iv
表目錄………………………………………………………………… vi
圖目錄…………………………………………………………………vii
第一章 緒論………………………………………………………………1
1.1、前言…………………………………………………………………1
1.2、研究動機與目的……………………………………………………1
1.3、論文架構……………………………………………………………4
第二章 元件製程與模擬系統架構………………………………………5
2.1、前言…………………………………………………………………5
2.2、元件結構……………………………………………………………5
2.3、實驗設備與材料……………………………………………………5
2.3.1、實驗設備介紹………………………………………………… 5
2.3.2、實驗材料介紹………………………………………………… 12
2.4、實驗流程…………………………………………………………12
2.4.1、基板切割……………………………………………………… 12
2.4.2、GaN/Sapphire基板清洗……………………………………… 12
2.4.3、液相沉積法成長絕緣層……………………………………… 13
2.4.3.1、溶液調配……………………………………………………14
2.4.3.2、成長氧化層…………………………………………………14
2.4.4、熱退火處理…………………………………………………… 15
2.4.5、電極製作……………………………………………………… 15
2.4.6、元件量測……………………………………………………… 15
2.5、模擬軟體介紹……………………………………………………15
2.6、電性模擬方法……………………………………………………16
第三章 氮化鎵上之SiO2在不同的退火溫度與厚度特性分析………17
3.1、前言………………………………………………………………17
3.2、退火後之電性分析………………………………………………17
3.3、較薄的氧化層退火後之電性分析………………………………22
3.4、小結………………………………………………………………27
第四章 Super Junction MOSFET模擬…………………………………28
4.1、前言………………………………………………………………28
4.2、元件模擬方法及結構……………………………………………28
4.3、元件模擬結果……………………………………………………31
4.4、元件模型分析……………………………………………………39
4.5、非理想下p n column結構之模擬結果…………………………45
4.6、小結………………………………………………………………56
第五章 結論……………………………………………………………57
參考文獻…………………………………………………………………58
簡歷………………………………………………………………………63

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