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研究生:洪嘉駿
研究生(外文):Jia-Jun Hong
論文名稱:氧化鋁鉿閘極介電層經電漿/熱退火處理之特性分析與可靠度之研究
論文名稱(外文):Electrical and Reliability Characteristics of Plasma/Thermal treated HfAlO High-k Gate Dielectrics
指導教授:林成利
指導教授(外文):Cheng-Li Lin
學位類別:碩士
校院名稱:逢甲大學
系所名稱:電子工程所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2010
畢業學年度:99
語文別:中文
論文頁數:142
中文關鍵詞:依時性介電層崩潰快速熱退火介電層沉積後之退火處理氧化鋁鉿二氧化鉿高介電係數介電層崩潰機制可靠度
外文關鍵詞:RTAHfAlOHfO2post-dielectric annealing (PDA)TDDBReliabilityBreakdown mechanismhigh-κ dielectric
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本論文探討CF4電漿處理(plasma treatment)及不同溫度之氮氣快速熱退火(RTA)處理對氧化鋁鉿(HfAlO)及二氧化鉿(HfO2)高介電質所造成的效應進行特性研究(此處RTA即為post-deposotion annealing, PDA)。本論文所研究的高介電質電容結構為氧化鋁鉿[TaN/HfAlO(16nm)/p-Si]、氧化鋁鉿/二氧化鉿[TaN/HfAlO(4nm)/HfO2(6nm)/p-Si]及二氧化鉿/氧化鋁鉿[TaN/HfO2(7nm)/HfAlO(6nm)/p-Si]三種結構。研究高介電質經過電漿處理與不同溫度氮氣熱退火處理之金氧半電容結構(metal insulator semiconductor, MIS)的基本電性、物性和可靠度研究。其內容包括閘極漏電流(I-V)分析、電容-電壓(C-V)特性分析、依時性介電層崩潰測試(TDDB)及介電層崩潰行為之物理機制的研究,以及找出最佳的氮氣熱退火處理溫度。
經由實驗結果分析,對單層HfAlO介電層結構的研究中,在400℃ PDA退火處理的電容遲滯之平帶電壓偏移值(flat-band voltage shift, ?幀FB)的結果分析,在進行PDA退火處理前有進行CF4電漿處理的高介電質,可改善?幀FB (0.21V vs. 0.35V)。另外,在最佳PDA退火處理溫度的研究方面,未經CF4電漿處理的樣品,其最佳的PDA退火處理溫度在400℃到700℃之間;而有經CF4電漿處理的樣品,其最佳的PDA退火處理溫度為900℃。
另外在堆疊結構方面,HfAlO/HfO2與HfO2/HfAlO二種結構的電容遲滯?幀FB都比單層結構HfAlO小。另外有經CF4電漿處理的樣品,可再進一步改善高介電質的電容遲滯。其中以堆疊結構HfO2/HfAlO經過CF4電漿處理後再進行700℃ PDA退火處理之?幀FB值為最小(0.074V),可得到最佳的結果。在最佳的的PDA退火處理溫度方面,沒有經CF4電漿處理的HfAlO/HfO2與HfO2/HfAlO兩種堆疊結構,其最佳PDA退火處理之溫度分別是700℃與900℃,而有經CF4電漿處理後再進行PDA退火處理,最佳的PDA退火處理溫度均為700℃。由以上分析,推測CF4電漿處理可改善二氧化鉿薄膜品質,使薄膜內部的缺陷(defects)與氧空缺(oxygen vacancies)減少。同時CF4電漿處理亦可有效降低閘極漏電流及提高崩潰電壓,同時減少介電層內之正陷阱電荷。
對高介電質的崩潰機制研究方面,首先對單層HfAlO(16 nm)高介電質崩潰機制進行研究。單層HfAlO(16 nm)高介電質先經過CF4電漿處理後,再經N2 PDA退火處理後,可提高崩潰電壓並且改善TDDB崩潰行為,推測由於氟離子修補薄膜內的缺陷或陷阱中心所致。對堆疊結構的崩潰行為研究方面,堆疊結構(HfO2/HfAlO/p-sub)與(HfAlO/HfO2/p-sub)相比較, HfO2在上層的堆疊結構(HfO2/HfAlO/p-sub)具有較高的崩潰電壓。綜合三種結構的電性分析,HfO2/HfAlO/p-sub之堆疊結構,具有較低的漏電流與較小的電容遲滯,以及較高的崩潰電壓與崩潰時間,因此整體特性最佳。
最後本論文亦研究高介電質(HfAlO)經靜電突波測試後之特性研究,本論文使用脈衝傳輸線所產生的突波(transmission line pulse, TLP)來模擬實際靜電測試,經由TLP偏壓測試後之電容結構(TaN/HfAlO/p-sub)的平帶電壓VFB往負電壓偏移。高介電質經過負電壓的靜電突波測試後,介電層內部靠近閘極端的區域有正電荷產生。其原因為施加TLP突波在閘極端,因而產生較大的電場,同時吸引正電荷,導致閘極高介電質正電荷捕捉快速增加。此外,在靠近閘極端之正電荷捕捉藉著陷阱輔助的碰撞行為產生離子電荷,因此其TDDB崩潰時間較短。
This thesis studies the effects of CF4 plasma treatment and rapid thermal annealing (RTA) in nitrogen (N2) ambient at various temperatures on HfAlO, HfAlO/HfO2, and HfO2/HfAlO gate stack structures with the whole dielectric film thickness of 16,10 and 13 nm, respectively. This RTA treatment is also called as the post-deposition annealing (PDA). A metal-insulator-semiconductor (MIS) structure was used to study the electrical characteristics in this thesis. These studies include leakage current (IV), capacitance-voltage (CV) characteristics, time dependent dielectric breakdown (TDDB), breakdown mechanism, and the optimal temperature of RTA treatment.
For the single layer of HfAlO dielectric with 400?aC PDA treatment, the film with CF4 plasma treatment before PDA tratement, the flat-band voltage shift (?幀FB) is reduced (0.21 vs. 0.35). The optimal temperatures of N2-PDA-treated HfAlO gate dielectrics with and without CF4 plasma treatment are in the range of 400?aC to 700?aC and 900?aC, respectively.
For the bi-layer stack structures of HfAlO/HfO2 and HfO2/HfAlO, the ?幀FBs are all smaller than that of the single layer structure of HfAlO. Additionally, the bi-layer stack dielectric with CF4 plasma treatment, the ?幀FB can also be reduced. Among these structures, the HfO2/HfAlO gate stack with CF4 plasma treatment before PDA treatment reveals the smallest ?幀FB (0.074V). The optimal temperature of N2 PDA treatment on HfAlO/HfO2 and HfO2/HfAlO stack structures without CF4 plasma treatment is 700?aC and 900?aC, respectively; in other hand, the optimal temperature of the gate stacks with CF4 plasma treatment is 700?aC. From the above analysis, the CF4 plasma can improve the film microstructure and reduce the defects and oxygen vacancies. In addition, the gate leakage current, breakdown voltage of TDDB testing are improved and reduce the positive oxide trapped charge in the dielectric film.
For dielectric breakdown of HfAlO, HfAlO/HfO2 and HfO2/HfAlO film strucutes, CF4 plasma treatment could improve the time to breakdown (TBD) and reveals less soft breakdown behavior. We presume the fluorine incorporated into the defects and oxide traps to reduce the traps assistant tunneling current and electron trapping/de-trapping behavior, thus, revealing superior electrical characteristics and TDDB realiabilty. By comparison of HfAlO/HfO2 and HfO2/HfAlO film structure, the HfO2/HfAlO stack structure reveals higher breakdown voltage than that of HfAlO/HfO2 film structure. Among these three dielectric film structures, the HfO2/HfAlO stack structure shows the lowest leakage current, smallest ?幀FB, highest breakdown voltage and longest TBD.
The last part of this thesis investigates the effects of electrostatic discharge (ESD) on HfAlO high-? gate dielectric. A transmission line pulse system is used to simulate the real electrostatic discharge. After the negative TLP stressing on gate terminal, the flat-band voltage (VFB) shifts in the negative direction of gate bias. This indicates more positive oxide charges appear in the dielectric film. Presumably, the large electrical field of TLP stressing creates many electrons and holes pairs in the film, and left many positive oxide charges in dielectric. As a result, the electrical characteristic is inferior and shorter TBD in reliability testing.
中文摘要 i
英文摘要 iv
致謝 viii
目錄 x
圖目錄 xiii
表目錄 xx
第一章 緒論
1.1研究背景 1
1.2高介電常數材料 3
1.3研究動機 4
1.4論文架構 6
第二章 MIS高介電係數薄膜元件的製備與電、物性分析
2.1製作氧化鋁鉿(16 nm)電容結構 12
2.2製作氧化鋁鉿(4 nm)/二氧化鉿(6 nm)電容結構 13
2.3 製作二氧化鉿(7 nm)/氧化鋁鉿(6 nm)電容結構 14
2.4製作二氧化鉿(3 nm)/二氧化矽(2 nm)電容結構 14
2.5製作二氧化鉿(3 nm)/氮氧化矽(2 nm)電容結構 15
2.6MIS結構電性量測方法
2.6.1電流對電壓(I-V)及TDDB特性曲線 15
2.6.2電容對電壓(C-V)特性曲線 16
2.7MIS物性與材料分析
2.7.1低掠角X光繞射儀(Glancing angle X-ray diffraction,
GIAXRD) 16
2.7.2穿透式電子顯微鏡(Transmission Electron Microscopy,
TEM) 17
2.7.3歐傑電子顯微鏡(Auger Electron Spectroscopy, AES) 17
第三章 氧化鋁鉿及不同堆疊層經過CF4電漿處理及熱退火(PDA)處理之特性研究
3.1氧化鋁鉿(16 nm)之電性探討 25
3.2氧化鋁鉿(4 nm)/二氧化鉿(6 nm)之雙層電性探討 28
3.3二氧化鉿(7 nm)/氧化鋁鉿(6 nm)之雙層電性探討 31
3.4二氧化鉿(3 nm)/二氧化矽(2 nm)之電性探討 34
3.5二氧化鉿(3 nm)/氮氧化矽(2 nm)之電性探討 36
3.6結論 37
第四章 靜電突波針對氧化鋁鉿經不同熱退火溫度(PDA)處理之電性
探討
4.1 介紹靜電突波相關實驗 88
4.2 實驗結果討論 89
4.3結論 91
第五章 總結論
5.1氧化鋁鉿(16 nm)之電性總結 95
5.2堆疊結構氧化鋁鉿(4 nm)/二氧化鉿(6 nm)之電性總結 95
5.3堆疊結構二氧化鉿(7 nm)/氧化鋁鉿(6 nm)之電性總結 96
5.4二氧化鉿(3 nm)之電性總結 96
5.5 氧化鋁鉿(16 nm)進行靜電突波之電性總結 97
5.6總結論 98
第六章 未來研究方向 104
參考文獻 106
個人簡歷 115
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