|
【1】D. Kahng and S.M.Sze, Bell Syst. Tech. J., Vol. 46, p.1288(1967)
【2】M. H. White, D.A.Adams, J.Bu, IEEE Circuits and Devices, Vol.16, No.4, pp.22-31(2000)
【3】W. J. Tsai, N. K. Zous, C. J. Lie, C. C. Liu, C. H. Chen, T. Wang, “Data retention behavior of a SONOS type two-bit storage flash memory cell”, in IEDM Tech. Dig. , pp.719-722, 2001
【4】M. Specht, U. Dorda, L. Dreeskomfeld, J Kretz, F. Hofmann, M. Stadele, R. J. Luyken, W. Rosner, H. Reisinger, E. Landgraf, T. Schulz, J. Hartwich, R. Kommling, and L. Risch, “20nm tri-gate SONOS memory cells with multi-level operation”, in IEDM Tech, Dig. , pp. 1083-1085, 2004.
【5】C. H. Lee, K. I. Choi, M. K. Cho, Y. H. Song, K. C. Park, and K. Kim, “A novel SONOS structure of SiO2/SiN/Al2O3 with TaN metal gate for multi-giga bit Flash memories,” in IEDM Tech. Dig., 2003, pp. 613–616.
【6】W. J. Tsai, N. K. Zous, C. J. Lie, C. C. Liu, C. H. Chen, T. Wang, “Data retention behavior of a SONOS type two-bit storage flash memory cell”, in IEDM Tech. Dig. , pp.719-722, 2001
【7】B. Eitan, P. Pavan, I. Bloom, E. Aloni, A. Frommer and D. Finzi, “NROM: A Novel Localized Trapping, 2-Bit Nonvolatile Memory Cell”, IEEE Electron Device Lett, Vol. 21, pp. 543-545, Nov. 2000.
【8】E. Lusky, G. Cohen, A Shappir, I. Bloom, and B. Eitan, “NROM the Multi Bit Localized Trapping Cell Scaling and Reliability”, Int. Symp. Advanced Devices and process, pp. 29-32, 2003
【9】B. Y. Choi, B. G. Park1, Y. K. Lee, S. K. Sung, T. Y. Kim, E. S. Cho, H. J. Cho, C. W. Oh, S. H. Kim, D. W. Kim, C. H. Lee, and D. Park, “Highly Scalable and Reliable 2-bit/cell SONOS Memory Transistor beyond 50nm NVM Technology Using Outer Sidewall Spacer Scheme with Damascene Gate Process”, VLSI Tech. Symp. , pp. 118-119, 2005
【10】S. Tiwari, F. Rana, K. Chan, H. Hanafi, C. Wei, and D. Buchanan, “Volatile and nonvolatile memories in silicon with nano-crystal storage”, in IEDM Tech. Dig. , pp. 521-524, 1995
【11】Jan De Blauwe, “Nanocrystal Nonvolatile Memory Devices”, IEEEE Trans. Nanotechnology, Vol. 1, No. 1. 2002
【12】Y. K. Lee, T. H. Kim, S. H. Lee, J. D. Lee, B. G. Park, “Twin-bit silicon-oxide-nitride-oxide-silicon (SONOS) memory by inverted sidewall patterning (TSM-ISP)”, IEEE Digest of Silicon Nanoelectronics Workshop, pp.92-93, 2003.
【13】E. Lusky, Y.Shacham-Diamand, I. Bloom, B. Eitan, “Electrons retention model for localized charge in oxide-nitride-oxide (ONO) dielectric”, IEEE Electron Dev. Lett. , vol.23, pp. 556-558, 2002
【14】Seong-Wan Ryu, Jong-Won Lee, Jin-Woo Han, Sungho Kim, and Yang-Kyu Choi, “Designed Workfunction Engineering of Double-Stacked Metal Nanocrystals for Nonvolatile Memory Application”, IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 56, NO. 3, MARCH 2009
【15】Jing Hao Chen, Ying Qian Wang, Won Jong Yoo, Senior Member, IEEE, Yee-Chia Yeo, Nonvolatile Flash Memory Device Using GeNanocrystals Embedded in HfAlO High-kTunneling and Control Oxides: Device Fabrication and Electrical Performance, IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 51, NO. 11, NOVEMBER 2004
【16】H. I. Hanafi, S. Tiwari, and I. Khan, “Fast and long retention-time nanocrystal memory,” IEEE Trans. Electron Devices, vol. 43, pp. 1553–1558, Sept. 1996.
【17】Y.-C. King, T.-J. King, and C. Hu, “MOS memory using germanium nanocrystals formed by thermal oxidation of Si Ge ,” in IEDM Tech. Dig., 1998, pp. 115–118.
【18】S. M. Sze, Physics of Semiconductor Devices, 2nd ed. New York: Wiley, 1981, pp. 849–850
【19】Y. Shi, K. Saito, H. Ishikuro, and T. Hiramoto, “Effects of interface traps on charges retention characteristics in silicon-quantum-dot-based metal-oxidesemiconductor diodes,” Jpn. J. Appl. Phys., vol. 38, pp. 425–428, Jan. 1999
【20】T. Usuki, T. Futatsugi, and N. Yokoyama, “A proposal of new floatinggate memory storing a small number of electrons with relatively long retention time at low voltage operations,” Microelectron. Eng., vol. 47, pp. 281–283, 1999.
【21】D.-W. Kim, T. Kim, and S. K. Banerjee, “Memory characterization of SiGe quantum dot Flash memories with HfO and SiO tunneling dielectrics,” IEEE Trans. Electron Devices, vol. 50, pp. 1823–1829, Sept.2003.
【22】Weihua Guan, Shibing Long, Ming Liu *, Qi Liu, Yuan Hu, Zhigang Li, Rui Jia, “Modeling of retention characteristics for metal and semiconductor nanocrystal memories”, Solid-State Electronics 51 (2007) 806–811.
【23】Konstantin K. Likharev, “Single-Electron Devices and Their Applications”, Proc. IEEE, vol. 87, pp. 606-632, April 1999.
【24】P.H. Yeh, L.J. Chena, P.T. Liu, D.Y. Wang, T.C. Changd, “Metal nanocrystals as charge storage nodes for nonvolatile memory devices”, Electrochimica Acta 52 (2007) 2920–2926.
【25】Z. Liu, C. Lee, V. Narayanan, G. Pei, and E. C. Kan, “Metal nanocrystal memories—Part I: Device design and fabrication,” IEEE Trans. Electron Devices, vol. 49, no. 9, pp. 1606–1613, Sep. 2002
【26】Z. Liu, C. Lee, V. Narayanan, G. Pei, and E. C. Kan, “Metal nanocrystal memories—Part II: Electrical characteristics,” IEEE Trans. Electron Devices, vol. 49, no. 9, pp. 1614–1622, Sep. 2002.
【27】C. Lee, J. Meteer, V. Narayanan, and E. C. Kan, “Self-assembly of metal nanocrystals on ultrathin oxide for nonvolatile memory applications,” J. Electron. Mater., vol. 34, no. 1, pp. 1–11, Jan. 2005.
【28】T.-H. Hou, C. Lee, V. Narayanan, U. Ganguly, and E. C. Kan, “Design optimization of metal nanocrystal memory—Part I: Nanocrystal array engineering,” IEEE Trans. Electron Devices, vol. 53, no. 12, pp. 3095– 3102, Dec. 2006.
【29】T.-H. Hou, C. Lee, V. Narayanan, U. Ganguly, and E. C. Kan, “Design optimization of metal nanocrystal memory—Part II: Gate-stack engineering,” IEEE Trans. Electron Devices, vol. 53, no. 12, pp. 3103–3108, Dec. 2006.
【30】J. J. Lee and D. L. Kwong, “Metal nanocrystal memory with high-k tunneling barrier for improved data retention,” IEEE Trans. Electron Devices, vol. 52, no. 4, pp. 507–511, Apr. 2005.
【31】S. K. Samanta, P. K. Singh, W. J. Yoo, G. Samudra, Y.-C. Yeo, L. K. Bera, and N. Balasubramanian, “Enhancement of memory window in short channel nonvolatile memory devices using double layer tungsten nanocrystals,” in IEDM Tech. Dig., 2005, pp. 170–173.
【32】T. Shan, C. Mao, Y. Liu, D. Q. Kelly, and S. K. Banerjee, “Proteinmediated nanocrystal assembly for flash memory fabrication,” IEEE Trans. Electron Devices, vol. 54, no. 3, pp. 433–438, Mar. 2007.
【33】K. S. Seol, S. J. Choi, J.-Y. Choi, E.-J. Jang, B.-K. Kim, S.-J. Park, D.-G. Cha, I.-Y. Song, J.-B. Park, Y. Park, and S.-H. Choi, “Pdnanocrystal- based nonvolatile memory structures with asymmetric SiO2/HfO2 tunnel barrier,” Appl. Phys. Lett., vol. 89, no. 8, pp. 083 109-1–083 109-3, Aug. 2006.
【34】Jong Jin Lee, Yoshinao Harada, Jung Woo Pyun and Dim-Lee Kwong, “Nickel nanocrystal formation on HfO2 dielectric for nonvolatile memory device applications”, Applied Physics Letters 86, 103505 (2005)
【35】Jin Lu, Ting-Chang Chang, Yu-Ting Chen, Jheng-Jie Huang, Po-Chun Yang, Shih-Ching Chen, Hui-Chun Huang, Der-Shin Gan, New-Jin Ho, Yi Shi, and Ann-Kuo Chu, Enhanced retention characteristic of NiSi2 /SiNx compound nanocrystal memory, Appl. Phys. Lett. 96, 262107 (2010)
【36】Chungho Lee, Tuo-Hung Hou, and Edwin Chih-Chuan Kan, Nonvolatile Memory With a Metal Nanocrystal/Nitride Heterogeneous Floating-Gate, Ieee Transactions On Electron Devices, Vol. 52, No. 12, December 2005
【37】S. K. Samanta, P. K. Singh, W. J. Yoo, G. Samudra, Y.-C. Yeo, L. K. Bera, and N. Balasubramanian, “Enhancement of memory window in short channel non-volatile memory devices using double layer tungsten nanocrystals,” in IEDM Tech. Dig., 2005, pp. 170–173
【38】C. Lee, A. Gorur-Seetharam, and E. C. Kan, “Operational and reliability comparison of discrete-storage nonvolatile memories: Advantages of single- and double-layer metal nanocrystals,” in IEDM Tech. Dig., 2003, pp. 22–26.
【39】S.-W. Ryu, Y.-K. Choi, C. B.Mo, S. H. Hong, P. K. Park, and S.-W. Kang, “A thickness modulation effect of HfO2 interfacial layer between doublestacked Ag nanocrystals for nonvolatile memory device applications,” J. Appl. Phys., vol. 101, no. 2, pp. 026 109-1–026 109-3, Jan. 2007.
【40】Chao-Cheng Lin, Ting-Chang Chang, Chun-Hao Tu, Wei-Ren Chen, Chih-Wei Hu, Simon M. Sze, Tseung-Yuen Tseng, Sheng-Chi Chen, and Jian-Yang Lin, “Improved reliability of Mo nanocrystal memory with ammonia plasma treatment”, Applied Physics Letters 94, 062106 (2009)
【41】Tsung-Kuei Kang, Ta-Chuan Liao, Cheng-Li Lin, and Wen-Fa Wu, “Effect of Nitrogen Plasma Treatment on Electrical Characteristics for Pd Nanocrystals in Nonvolatile Memory”, Japanese Journal of Applied Physics 49 (2010) 086202
【42】M. Houssa, M. Tuominen, M. Naili, V. Afanas’ev and A. Stesmans, S. Haukka, M. M. Heyns, “Trap-assisted tunneling in high permittivity gate dielectric stacks”, J. Appl. Phys. 87 (2000) 8615
【43】X.F.Zheng, W.D.Zhang B. Govoreanu(2), J.F.Zhang, J. van Houdt,” A discharge-based multi-pulse technique (DMP) for probing electron trap energy distribution in high-k materials for Flash memory application, IEDM.2009(5424403)
【44】International Technology Roadmap for Semiconductors
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