臺灣博碩士論文加值系統

目前的電子應用產品如：智慧型手機與車用電子皆是十分複雜的系統，使得現今的暫存器轉移階層(register transfer level, RTL)設計流程面臨嚴峻的挑戰。 因此，電路設計者必須付諸更多努力與代價，才能使產品即時上市。
電子系統層級(electronic system level, ESL) 是一個全新的晶片設計方法。此方法能夠大為降低設計晶片的複雜度與困難，其原因為：相對於暫存器轉移階層設計方式，電子系統層級的晶片設計與驗證十分有效率。另一方面，軟體與硬體在電子系統層級可以協同設計或模擬，大大地縮短所需的設計時程。然而，電子系統層級與暫存器轉移階層的設計流程仍然存在一個缺口，因此需一個硬體編譯器轉換並整合這兩種不同的設計方式。
高階合成(high level synthesis, HLS) 根據給定的設計目標，將電路之行為描述轉換成暫存器轉移階層描述。許多實體問題如：高功率消耗與低可測試性是源於不好的暫存器轉移階層架構，這些問題應於高階合成時解決。本篇論文開發一個高階合成系統，針對不同的設計條件與目標，產生適合並滿足給定設計條件的暫存器轉移階層架構。此高階合成系統包含數個合成方法。第三章提出一個以可測試性為導向的合成方法。第四章在功能模式與測試模式下，考量溫度感知之電路設計。第五章提出一個整合非零時序差異管理 (clock skew management)與以低功率為目標的合成方法。

Modern consumer electronic applications, including smart phone and automotive electronics, become very complicated. The time-to-market requirement of such applications has become a serious challenge for contemporary register transfer level (RTL) design flow.
Electronic system level (ESL) is a novel design methodology that can reduce designers’ efforts greatly since describing and verifying a design in ESL is more efficient than in RTL. On the other hand, co-design and co-simulation of software and hardware can be carried out in ESL; therefore design cycle can be shortened greatly. However, a gap exists between ESL flow and RTL flow; a hardware complier is required to transform and integrate these two different design methods.
High level synthesis (HLS) generates RTL descriptions from behavioral descriptions according to given design targets. Many physical problems like high power consumption and low testability are caused by bad RTL architectures, and these problems should be solved during high level synthesis. In this dissertation, we develop an HLS system that considers various design targets to generate appropriate RTL architectures that meet given design constraints. Several synthesis methodologies are given in our HLS system. A testability driven synthesis method is given in Chapter 3. The method in Chapter 4 considers thermal issue in both normal operations and during test to achieve a thermal aware design. A low power synthesis method integrated with clock skew management is given in Chapter 5.

1. Introduction 1
1.1. ESL Methodology 3
1.2. High Level Synthesis 5
1.3. High Level Test Synthesis 7
1.4. Overview and Contribution 8
1.4.1. HLTS for Hierarchical Delay Fault Testability 9
1.4.2. Thermal Safe HLTS for Hierarchical Testability 9
1.4.3. Low Power HLS with Clock Skew Management 10
1.4.4. Organization 10
2. Background 11
2.1. Behavioral Model 11
2.1.1. Acceptable Input Description 11
2.1.2. Control Data Flow Graph (CDFG) 13
2.2. Scheduling 14
2.2.1. ASAP and ALAP Scheduling 15
2.2.2. List Scheduling 16
2.2.3. Integer Linear Programming (ILP) Scheduling 18
2.3. Resource Binding 20
2.3.1. Operation / Variable Lifetime 20
2.3.2. Left Edge Algorithm (LEA) 22
2.3.3. ILP Based Resource Binding 23
2.4. Datapath and Controller 24
2.5. Circuit Testing 25
2.5.1. Design for Testability (DFT) 25
2.5.2. Fault Model 26
2.5.3. Hierarchical Testing 27
2.6. Clock Skew Scheduling (CSS) 30
2.6.1. Timing Constraints in Synchronous Circuit 30
2.6.2. Basic Idea of CSS 31
2.6.3. Clock Skew Scheduling in SDFG 32
3. HLTS for Hierarchical Delay Fault Testability 34
3.1. Related Works 34
3.2. Delay Testability Analysis for DFG 36
3.2.1. Behavioral View 36
3.2.2. Solving Equations 38
3.3. Synthesis Methodology 42
3.3.1. Definition 43
3.3.2. Redundant Operation Insertion 45
3.3.2.1. Redundant Operation Reduction 45
3.3.2.2. CPIVS Selection 46
3.3.2.3. Location of the Redundant Operation 46
3.3.3. Overall Flow 47
3.3.4. An Illustrative Example 49
3.4. Datapath Circuit Test 50
3.4.1. Module Test 51
3.4.2. Multiplexer-based Interconnect Test 51
3.4.3. Register Test 52
3.5. DFT Insertion for Delay Fault Testability 53
3.5.1. Type-I DFT 53
3.5.2. Type-II DFT 54
3.6. Experimental Results 56
3.6.1. Area 56
3.6.2. Test Without DFT Insertion 59
3.6.3. Test with DFT Insertion 61
3.6.4. Synthesis Methods vs. Delay Fault Coverage 65
3.7. Conclusion of this Chapter 66
4. Thermal Safe HLTS for Hierarchical Testability 68
4.1. Related Works 68
4.2. Motivation 69
4.3. Problem Description 72
4.4. Simplified Thermal Model 73
4.4.1. Power Density vs. Temperature 73
4.4.2. Average Power Density vs. Temperature 75
4.5. Synthesis Methodology 76
4.5.1. Overall Flow 76
4.5.2. Synthesis Procedure 77
4.6. Experimental Results 79
4.6.1. Temperature Results 80
4.6.2. Area Comparison 81
4.6.3. Test Time Comparison 81
4.7. Conclusion of this Chapter 82
5. Low Power HLS with Clock Skew Management 83
5.1. Related Works 83
5.2. Power Reduction by Clock Skew Scheduling 85
5.2.1. Module Types vs. Power Consumption 86
5.2.2. Reallocation 86
5.3. Effect of Resource Binding on Timing Graph 88
5.3.1. Register Binding vs. Timing Graph 89
5.3.2. Module Binding vs. Timing Graph 90
5.4. Clock Skew Management 92
5.4.1. Clock Skew vs. Clock Period in HLS 93
5.4.2. Proposed Clock Skew Management 94
5.5. Low Power Synthesis Flow 96
5.5.1. Overall Synthesis Flow 96
5.5.2. MILP Based Module Binding 97
5.5.3. Heuristic of Module Binding 100
5.5.4. Register Binding and Interconnect Synthesis 104
5.5.5. Controller Synthesis 104
5.6. Experimental Results 105
5.6.1. Power Results 106
5.6.2. Impact of Reallocation 108
5.7. Conclusion of this Chapter 110
6. Conclusions 111
6.1. High Level Test Synthesis Methodology 111
6.2. Thermal Safe Test Synthesis 112
6.3. Low Power Synthesis for Nonzero Skew Design 113
6.4. Future Works 113
Reference 114

[1]Moore’s Law. Available: www.greentechmedia.com/content/images/articles/varian
-moores-law-graph.jpg
[2]A. Parker, D. Thomas, D. Siewiorek, M. Barbacci, L. Hafer, G. Leive, and J. Kim, ‘‘The CMU design automation system - an example of automated data path design,’’ in Proc. Des. Autom. Conf. (DAC), pp. 73-80, 1979.
[3]Catapult C Synthesis Datasheet, Mentor Graphics Corporation, 2010. Available: http://www.mentor.com/
[4]Introduction to Synphony HLS White Paper, Synopsys Inc., 2009. Available: http://www.synopsys.com/home.aspx
[5]C-to-Silicon compiler’s Datasheet, Cadence Design Systems Inc., 2008. Available: http://www.cadence.com/us/pages/default.aspx
[6]CynthesizerTM Datasheet, Forte Design Systems, 2008. Available: http://www.forteds.com/
[7]System C Language Reference Manual, IEEE Standard 1666, 2005. Available: http://www.systemc.org
[8]Transaction Level Modeling (TLM 2.0), OSCI Standard, 2008. Available: http://www.systemc.org
[9]P. G. Paulin and J. P. Knight, ‘‘Force-directed scheduling for the behavioral synthesis of ASICs,’’ IEEE Trans. on Comput.-Aided Des. of Integr. Circuits and Syst., vol. 8, no. 6, pp. 661-679, 1989.
[10]P. Coussy and A. Morawiec, eds., High-Level Synthesis: From Algorithm to Digital Circuit, Springer, 2008.
[11]D. D. Gajski, N. D. Dutt, A. C.-H. Wu, and S. Y.-L. Lin, High Level Synthesis: An Introduction to Chip and System Design, Springer, 1992.
[12]G. De Micheli, Synthesis and Optimization of Digital Circuits, McGraw-Hill, 1994.
[13]R. Camposano and W. Wolf, eds., High-Level VLSI Synthesis, Springer, 1991.
[14]D. W. Knapp, Behavioral Synthesis: Digital System Design Using the Synopsys Behavioral Compiler, Prentice Hall, 1996.
[15]G. Martin and G. Smith, “High-level synthesis: past, present, and future,” IEEE Des. and Test of Comput., vol. 26, no. 4, pp. 18-25, 2009.
[16]Y. Huang, C.-C. Tsai, N. Mukherjee, O. Samman, D. Devries, W.-T. Cheng, and S. M. Reddy, “On RTL scan design,” in Proc. Int. Test Conf. (ITC), pp. 728-737, 2001.
[17]H. F. Ko and N. Nicolici, “RTL scan design for skewed-load at-speed test under power constraints,” in Proc. Int. Conf. on Comput. Des. (ICCD), pp. 237-242, 2006.
[18]H. F. Ko and N. Nicolici, “Functional Illinois scan design at RTL,” in Proc. Int. Conf. on Comput. Des. (ICCD), pp. 78-81, 2004.
[19]D. Ku and G. De Micheli, “High-level synthesis and optimization strategies in hercules and hebe,” in Proc. Euro ASIC (EASIC), pp. 124-129, 1990.
[20]M. T.-C. Lee, High-Level Test Synthesis of Digital VLSI Circuits, Artech House, 1997.
[21]T.-C. Lee, W. H. Wolf, and N. K. Jha, “Behavioral synthesis for easy testability in data path scheduling,” in Proc. Int. Conf. on Comput.-Aided Des. (ICCAD), pp. 616-619, 1992.
[22]T.-C. Lee, W. H. Wolf, N. K. Jha, and J. M. Acken, “Behavioral synthesis for easy testability in data path allocation,” in Proc. Int. Conf. on Comput. Des. (ICCD), pp. 29-32, 1992.
[23]T.-C. Lee, N. K. Jha, and W. H. Wolf, “A conditional resource sharing method for behavioral synthesis of highly testable data paths,” in Proc. Int. Test Conf. (ITC), pp. 744-752, 1993.
[24]T. Lin, S. Dong, S. Chen, Y. Ma, O. He, and S. Goto, “Novel and efficient min cut based voltage assignment in gate level,” in Proc. Int. Symp. on Quality Electronic Des. (ISQED), pp. 1-6, 2011.
[25]D. Chen, J. Cong, C. Dong, L. He, F. Li, and C.-C. Peng, “Technology mapping and clustering for FPGA architectures with dual supply voltages,” IEEE Trans. on Comput.-Aided Des. of Integr. Circuits and Syst., vol. 29, no. 11, pp. 1709-1722, 2010.
[26]S. Bijansky, S. K. Lee, and A. Aziz, “TuneLogic: post-silicon tuning of dual-vdd designs,” in Proc. Int. Symp. on Quality Electronic Des. (ISQED), pp. 394-400, 2009.
[27]A. Kumar and M. Anis, “Dual-threshold CAD framework for subthreshold leakage power aware FPGAs,” IEEE Trans. on Comput.-Aided Des. of Integr. Circuits and Syst., vol. 26, no. 1, pp. 53-66, 2007.
[28]S. A. Tawfik and V. Kursun, “Low power and robust 7T dual-vt SRAM circuit,” in Proc. Int. Symp. on Circuits and Syst. (ISCAS), pp. 1452-1455, 2008.
[29]J. Kim and Y. Shin, “Minimizing leakage power in sequential circuits by using mixed vt flip-flops,” in Proc. Int. Conf. on Comput.-Aided Des. (ICCAD), pp. 797-802, 2007.
[30]C. E. Leiserson, F. M. Rose, and J. B. Saxe, “Optimizing synchronous circuitry by retiming,” in Proc. Caltech Conf. on VLSI, 1983.
[31]J. P. Fishburn, “Clock skew optimization,” IEEE Trans. on Comput., vol. 39, no 7, pp. 945-951, 1990.
[32]B. M. Pangrle and D. D. Gajski, “Slicer: a state synthesizer for intelligent silicon compilation,” in Proc. Int. Conf. on Comput.-Aided Des. (ICCAD), pp. 536-541, 1987.
[33]E. F. Girczyc, R. J. A. Buhr, and J. P. Knight, “Applicability of a subset of Ada as an algorithmic hardware description language for graph-based hardware compilation,” IEEE Trans. on Comput.-Aided Des. of Integr. Circuits and Syst., vol. 4, no. 2, pp. 134-142, 1985.
[34]P. G. Paulin and J. P. Knight, “Scheduling and binding algorithm for high level synthesis,” in Proc. Des. Autom. Conf. (DAC), pp. 25-29, 1989.
[35]A. Schrijver, Theory of Linear and Integer Programming, Wiley, 1998.
[36]T. H. Cormen, C. E. Leiserson, R. L. Rivest, and C. Stein, Introduction to Algorithm, 2nd ed., MIT press, 2001, chapter 34.
[37]S. Chaudhuri and R. A. Walker, “ILP-based scheduling with time and resource constraints in high level synthesis,” in Proc. Int. Conf. on VLSI Des. (ICVD), pp. 17-20, 1994.
[38]C.-T. Huang, Y.-C. Hsu, and Y.-L. Lin, “Optimum and heuristic data path scheduling under resource constraints,” in Proc. Des. Autom. Conf. (DAC), pp. 65-70, 1990.
[39]G. Lucas and D. Chen, “Variation-aware layout-driven scheduling for performance yield optimization, in Proc. Int. Conf. on Comput.-Aided Des. (ICCAD), pp. 17-24, 2010.
[40]M. Raghavachari, “A constructive method to recognize the total unimodularity of a matrix,” Journal on Mathematical Methods of Operations Research, vol. 20, no. 1, pp. 59–61, 1976.
[41]J. Cong and Z. Zhang, “An efficient and versatile scheduling algorithm based on SDC formulation, in Proc. Des. Autom. Conf. (DAC), pp. 433-438, 2006.
[42]J. Cong, B. Liu, and Z. Zhang, “Scheduling with soft constraints,” in Proc. Int. Conf. on Comput.-Aided Des. (ICCAD), pp. 47-54, 2009.
[43]A. Hashimoto and J. Stevens, “Wire routing by optimizing channel assignment within large apertures,” in Proc. Des. Autom. Workshop. (DAC), pp. 155-169, 1971.
[44]F. J. Kurdahi and A. C. Parker, “REAL: a program for register allocation,” in Proc. Des. Autom. Conf. (DAC), pp. 210-215, 1987.
[45]C.-Y. Huang, Y.-S. Chen, Y.-L. Lin, and Y.-C. Hsu, “Data path allocation based on bipartite weighted matching,” in Proc. Des. Autom. Conf. (DAC), pp. 499-504, 1990.
[46]J. Munkres, “Algorithms for the assignment and transportation problems,” Journal on the Society for Industrial and Applied Mathematics, vol. 5, no. 1, pp. 32–38, 1957.
[47]R. K. Ahuja, T. L. Magnanti, and J. B. Orlin, Network Flows: Theory, Algorithms and Applications, Prentice Hall, 1993.
[48]J. Cong and J. Xu, “Simultaneous FU and register binding based on network flow method,” in Proc. Des. Autom. and Test in Europe (DATE), pp. 1057-1063, 2008.
[49]V. D. Agrawal, C. R. Kime, and K. K. Saluja, “A tutorial on built-in-self-test, part 2: application,” IEEE Des. and Test of Comput., vol. 10, no. 2, pp. 69-77, 1993.
[50]M. J. Y. Willaims and J. B. Angell, “Enhancing testability of large-scale integrated circuits via test points and additional logic,” IEEE Trans. on Comput., vol. C-22, no 7, pp. 46-60, 1973.
[51]M. L. Bushnell and V. D. Agrawal, Essentials of Electronic Testing for Digital, Memory & Mixed-Signal VLSI Circuits, Springer, 2000, chapter 4.
[52]M. L. Bushnell and V. D. Agrawal, Essentials of Electronic Testing for Digital, Memory & Mixed-Signal VLSI Circuits, Springer, 2000, chapter 12.
[53]K.-T. Cheng, S. Devadas, and K. Keutzer, “A partial enhanced-scan approach to robust delay-fault test generation for sequential circuits,” in Proc. Int. Test Conf. (ITC), 1991.
[54]J. Savir and S. Patel, “Scan-based transition test,” IEEE Trans. on Comput.-Aided Des. of Integr. Circuits and Syst., vol. 12, no. 8, pp. 1232-1241, 1993.
[55]J. Savir and S. Patel, “Broad-side delay test,” IEEE Trans. on Comput.-Aided Des. of Integr. Circuits and Syst., vol. 13, no. 8, pp. 1057-1064, 1994.
[56]B. T. Murray and J. P. Hayes, “Hierarchical test generation using precomputed tests for modules,” IEEE Trans. on Comput.-Aided Des. of Integr. Circuits and Syst., vol. 9, no. 6, pp. 594-603, 1990.
[57]T.-H Chao, Y.-C. Hsu, J.-M. Ho, and A. B. Kahng, “Zero skew clock routing with minimum wirelength,” IEEE Trans. on Circuits and Syst. II: Analog and Digital Signal Processing, vol. 39, no. 11, pp. 799-814, 1992.
[58]J.-L. Tsai, T.-H. Chen, C. C.-P. Chen, “Zero skew clock-tree optimization with buffer insertion/sizing and wire sizing,” IEEE Trans. on Comput.-Aided Des. of Integr. Circuits and Syst., vol. 23, no. 4, pp. 565-572, 2004.
[59]C.-M. Chang, S.-H. Huang, Y.-K. Ho, J.-Z. Lin, H.-P. Wang, and Y.-S. Lu, “Type-matching clock tree for zero skew clock gating,” in Proc. Des. Autom. Conf. (DAC), pp. 714-719, 2008.
[60]R. B. Deokar and S. S. Sapatnekar, “A graph-theoretic approach to clock skew optimization,” in Proc. Int. Symp. on Circuits and Syst. (ISCAS), pp. 407-410, 1994.
[61]K. Ravindran, A. Kuehlmann, and E. Sentovich, “Multi-domain clock skew scheduling,” in Proc. Int. Conf. on Comput.-Aided Des. (ICCAD), pp. 801-808, 2003.
[62]S.-H. Huang and C.-H. Cheng, “Minimum-period register binding,” IEEE Trans. on Comput.-Aided Des. of Integr. Circuits and Syst., vol. 28, no. 8, pp. 1265-1269, 2009.
[63]A. Krstic and K.-T. Cheng, Delay Fault Testing for VLSI Circuits, Kluwer Academic Publishers, 1998.
[64]P. Girard, C. Landrault, V. Moreda, and S. Pravossoudovitch, “An optimized BIST test pattern generator for delay testing,” in Proc. VLSI Test Symp. (VTS), pp. 94-100, 1997.
[65]R. B. Norwood and E. J. McCluskey, “High-level synthesis for orthogonal scan,” in Proc. VLSI Test Symp. (VTS), pp. 370-375, 1997.
[66]V. Fernandez and P. Sanchez, “Partial scan high-level synthesis,” in Proc. European Des. and Test Conf. (EDTC), pp. 481-485, 1996.
[67]S. Dey and M. Potkonjak, “Non-scan design-for-testability of RT-level data paths,” in Proc. Int. Conf. on Comput.-Aided Des. (ICCAD), pp. 640-645, 1994.
[68]V. Chickermane, J. Lee, and J. H. Patel, “Addressing design for testability at the architectural level,” IEEE Trans. on Comput.-Aided Des. of Integr. Circuits and Syst., vol. 13, no. 7, pp.920-934, 1996.
[69]S. Bhatia and N. K. Jha, “Integration of hierarchical test generation with behavioral synthesis of controller and data path circuits,” IEEE Trans. on Very Large Scale Integr. (VLSI) Syst., vol. 6, no. 4, pp. 608-619, 1998.
[70]I. Ghosh, A. Raghunathan, and N. K. Jha, “Design for hierarchical testability of RTL circuits obtained by behavioral synthesis,” IEEE Trans. on Comput.-Aided Des. of Integr. Circuits and Syst., vol. 16, no. 9, pp. 1001-1014, 1997.
[71]S. Ohtake, H. Wada, T. Masuzawa, and H. Fujiwara, “A non-scan DFT method at register-transfer level to achieve complete fault efficiency,” in Proc. Asia and South Pacific Des. Autom. Conf. (ASPDAC), pp. 599-604, 2000.
[72]H. Iwata, T. Yoneda, S. Ohtake, and H. Fujiwara, “A DFT method for RTL data paths based on partially strong testability to guarantee complete fault efficiency,” in Proc. Asian Test Symp. (ATS), pp. 306-311, 2005.
[73]Y. Makris, J. Collins, A. Orailoglu, and P. Vishakantaiah, “TRANSPARENT: a system for RTL testability analysis, DFT guidance and hierarchical test generation,” in Proc. Custom Integr. Circuit (CICC), pp. 159-162, 1999.
[74]L. Lingappan, S. Ravi, and N. K. Jha, “Satisfiability-based test generation for nonseparable RTL controller-datapath circuits,” IEEE Trans. on Comput.-Aided Des. of Integr. Circuits and Syst., vol. 25, no. 3, pp. 544-557, 2006.
[75]L. Lingappan and N. K. Jha, “Satisfiability-based automatic test program generation and design for testability for microprocessors,” IEEE Trans. on Very Large Scale Integr. (VLSI) Syst., vol. 15, no. 5, pp. 518-530, 2007.
[76]Md. Altaf-Ul-Amin, S. Ohtake, and H. Fujiwara, “Design for hierarchical two-pattern testability of data paths,” in Proc. Asian Test Symp. (ATS), pp. 11-16, 2001.
[77]Y. Yoshikaw, S. Ohtake, M. Inoue, and H. Fujiwara, “Design for testability based on single-port-change delay testing for data paths,” in Proc. Asian Test Symp. (ATS), pp. 254-259, 2005.
[78]CLAPACK. Available: www.nelib.org/clapack/
[79]H. K. Lee and D. S. Ha, "On the generation of test patterns for combinational circuits," Technical Report no. 12_93, Dep''t of Electrical Eng., Virginia Polytechnic Institute and State University.
[80]Y.-W. Wu, C.-L. Yang, P.-H. Yuh, and Y.-W. Chang, “Joint exploration of architectural and physical design spaces with thermal consideration,” in Proc. Int. Symp. on Low Power Electronics and Des. (ISLPED), pp. 123-126, 2005.
[81]C.-T. Chu, X. Y. Zhang, L. He, and T. T. Jing, “Temperature aware microprocessor floorplanning considering application dependent power load,” in Proc. Int. Conf. on Comput.-Aided Des. (ICCAD), pp. 586-589, 2007.
[82]R. Mukherjee and S. O. Memik, “Physical aware frequency selection for dynamic thermal management in multi-core systems,” in Proc. Int. Conf. on Comput.-Aided Des. (ICCAD), pp. 547-552, 2006.
[83]Y. Lin and Q. Gang, “ALT-DVS: dynamic voltage scaling with awareness of leakage and temperature for real-time systems,” in Proc. NASA/ESA Conf. on Adaptive Hardware and Syst. (AHS), pp. 660-670, 2007.
[84]R. Mukherjee, S. O. Memik, and G. Memik, “Temperature-aware resource allocation and binding in high-level synthesis,” in Proc. Des. Autom. Conf. (DAC), pp. 196-201, 2005.
[85]R. Mukherjee, S. O. Memik, and G. Memik, “Peak temperature control and leakage reduction binding in high level synthesis,” in Proc. Int. Symp. on Low Power Electronics and Des. (ISLPED), pp. 251-256, 2005.
[86]R. Mukherjee and S. O. Memik, “An integrated approach to thermal management in high-level synthesis,” IEEE Trans. on Very Large Scale Integr. (VLSI) Syst., vol. 14, no. 11, pp. 1165-1174, 2006.
[87]M. Ni and S. O. Memik, “Thermal-induced leakage power optimization by redundant resource allocation,” in Proc. Int. Conf. on Comput.-Aided Des. (ICCAD), pp. 297-302, 2006.
[88]J. Yu, Q. Zhou, G. Qu, and J. Bian, “ Behavioral level dual-vth design for reduced leakage power with thermal awareness,” in Proc. Des. Autom. and Test in Europe (DATE), pp. 1261-1266, 2010.
[89]V. Krishnan and S. Katkoori, “TABS: temperature-aware layout-driven behavioral synthesis,” IEEE Trans. on Very Large Scale Integr. (VLSI) Syst., vol. 18, no. 12, pp. 1649-1659, 2010.
[90]P. Rosinger, B. M. Al-Hashimi, and K. Chakrabarty, “Thermal-safe test scheduling for core-based system-on-chip integrated circuits,” IEEE Trans. on Comput.-Aided Des. of Integr. Circuits and Syst., vol. 25, no. 11, pp. 2502-2512, 2006.
[91]C. Liu and V. Iyengar, “Test scheduling with thermal optimization for network-on-chip systems using variable-rate on-chip clocking,” in Proc. Des. Autom. and Test in Europe (DATE), 2006.
[92]Z. He, Z. Peng, and P. Eles, “Multi-temperature testing for core-based system-on-chip,” in Proc. Des. Autom. and Test in Europe (DATE), pp. 208-213, 2010.
[93]S. A. Bota, J. L. Rossello, C. De Benito, A. Keshavarzi, and J. Segura, “Impact of thermal gradients on clock skew and testing,” IEEE Des. and Test of Comput., vol. 23, no. 5, pp. 414-424, 2006.
[94]M. Cho and D. Z. Pan, “PEAKASO: peak-temperature aware scan-vector optimization,” in Proc. VLSI Test Symp. (VTS), 2006.
[95]S.-J. Wang and T.-H. Yeh, “High-level test synthesis for delay fault testability,” in Proc. Des. Autom. and Test in Europe (DATE), pp. 45-50, 2007.
[96]S.-J. Wang and T.-H. Yeh, “High-level test synthesis with hierarchical test generation for delay-fault testability,” IEEE Trans. on Comput.-Aided Des. of Integr. Circuits and Syst., vol. 28, no. 10, pp. 1583-1596, 2009.
[97]Y.-C. Chang, Y.-W. Chang, G.-M. Wu, and S.-W. Wu, “B*-trees: a new representation for non-slicing floorplans,” in Proc. Des. Autom. Conf. (DAC), pp. 458-463, 2000.
[98]S. Gupta and F. N. Najm, “Analytical models for RTL power estimation of combinational and sequential circuits,” IEEE Trans. on Comput.-Aided Des. of Integr. Circuits and Syst., vol. 19, no. 7, pp. 808-814, 2000.
[99]W. Huang, M. R. Stan, K. Skadron, K. Sankaranarayanan, S. Ghosh, and S. Velusamy, “Compact thermal modeling for temperature- aware design,” in Proc. Des. Autom. Conf. (DAC), pp.878-883, 2004.
[100]S. Im and K. Banerjee, “Full chip thermal analysis of planar (2-d) and vertically integrated (3-d) high performance ICs,” in Proc. Int. Electron Devices Meeting (IEDM), pp.727-730, 2000.
[101]N. S. Kim, T. Austin, D. Baauw, T. Mudge, K. Flautner, J. S. Hu, M. J. Irwin, M. Kandemir, and V. Narayanan, “Leakage current: Moore’s law meets static power,” IEEE Comput., vol. 36, no. 12, pp. 68-75, 2003.
[102]H.-O. Kim, Y. Shin, H. Kim, and I. Eo, “Physical design methodology of power gating circuits for standard-cell-based design,” in Proc. Des. Autom. Conf. (DAC), pp. 109-112, 2006.
[103]Y. Lee, D.-K. Jeong, and T. Kim, “Simultaneous control of power/ground current, wakeup time and transistor overhead in power gated circuits,” in Proc. Int. Conf. on Comput.-Aided Des. (ICCAD), pp. 169-172, 2008.
[104]G. Feng and J. P. Hayes, “Exact and heuristic approaches to input vector control for leakage power reduction,” IEEE Trans. on Comput.-Aided Des. of Integr. Circuits and Syst., vol. 25, no. 11, pp. 2564-2571, 2006.
[105]L. Yuan and G. Qu, “A combined gate replacement and input vector control approach for leakage current reduction,” IEEE Trans. on Very Large Scale Integr. (VLSI) Syst., vol. 14, no. 2, pp. 173-182, 2006.
[106]W.-T. Shine and C. Chakrabarti, “Low-power scheduling with resources operating at multiple voltages,” IEEE Trans. on Circuits and Syst. II: Analog and Digital Signal Processing, vol. 47, no. 6, pp. 536-543, 2000.
[107]M. Hariyama, T. Aoyama, and M. Kameyama, “Genetic approach to minimizing energy consumption of VLSI processors using multiple supply voltages,” IEEE Trans. on Comput., vol. 54, no. 6, pp. 642-650, 2005.
[108]X. Xing and C. C. Jong, “Multivoltage multifrequency low-energy synthesis for functionally pipelined datapath,” IEEE Trans. on Very Large Scale Integr. (VLSI) Syst., vol. 17, no. 9, pp. 1348-1352, 2009.
[109]K. S. Khouri and N. K. Jha, “Leakage power analysis and reduction during behavioral synthesis,” IEEE Trans. on Very Large Scale Integr. (VLSI) Syst., vol. 10, no. 6, pp. 876-885, 2002.
[110]X. Tang, H. Zhou, and P. Banerjee, “Leakage power optimization with dual-Vth library in high-level synthesis,” in Proc. Des. Autom. Conf. (DAC), pp. 202-207, 2005.
[111]J. M. Chang and M. Pedram, “Module assignment for low-power,” in Proc. European Des. Autom. Conf. (EDAC), pp. 376-381, 1996.
[112]D. W.-C. Lam, C. K. Koh, and A. C.-W. Tsao, “Power supply noise suppression via clock skew scheduling,” in Proc. Int. Symp. on Quality Electronic Des. (ISQED), pp. 355-360, 2002.
[113]M. Ni and S. O. Memik, “Leakage power-aware clock skew scheduling: Converting stolen time into leakage power reduction,” in Proc. Des. Autom. Conf. (DAC), pp. 610-613, 2008.
[114]M. Ni and S. O. Memik, “Early planning for clock skew scheduling during register binding,” in Proc. Int. Conf. on Comput.-Aided Des. (ICCAD), pp. 429-434, 2007.
[115]S.-H. Huang and C.-H. Cheng, “Timing driven power gating in high-level synthesis,” in Proc. Asia and South Pacific Des. Autom. Conf. (ASPDAC), pp. 173-178, 2009.
[116]M. Ni and S. O. Memik, “A fast heuristic algorithm for multidomain clock skew scheduling”, IEEE Trans. on Very Large Scale Integr. (VLSI) Syst., vol. 18, no. 4, pp. 630-637, 2010.
[117]T. Obata and M. Kaneko, “Control signal skew scheduling in RT level datapath synthesis,” in Proc. Midwest Symp. on Circuits and Syst. (MWSCAS), pp. 1087-1090, 2005.
[118]T. Obata and M. Kaneko, “Concurrent skew and control step assignments in RT-level datapath synthesis,” in Proc. Int. Symp. on Circuits and Syst. (ISCAS), pp. 2018-2021, 2008.
[119]Predictive Technology Model. Available: http://www.eas.asu.edu/~ptm/