跳到主要內容

臺灣博碩士論文加值系統

(34.204.169.230) 您好!臺灣時間:2024/03/04 10:40
字體大小: 字級放大   字級縮小   預設字形  
回查詢結果 :::

詳目顯示

我願授權國圖
: 
twitterline
研究生:洪毓章
研究生(外文):Yu-Chang Hung
論文名稱:針對三維晶片之未接合可測試性時脈樹最佳化
論文名稱(外文):Clock Tree Optimization with Prebond Testability in 3D IC
指導教授:王行健
口試委員:李淑敏黃宗柱鄭經華
口試日期:2011-07-18
學位類別:碩士
校院名稱:國立中興大學
系所名稱:資訊科學與工程學系所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2011
畢業學年度:99
語文別:中文
論文頁數:44
中文關鍵詞:三維晶片未接合測試時脈樹
外文關鍵詞:3D ICPre-bond TestClock Tree
相關次數:
  • 被引用被引用:0
  • 點閱點閱:131
  • 評分評分:
  • 下載下載:0
  • 收藏至我的研究室書目清單書目收藏:0
現今數位電路的功能日漸強大,構造越來越複雜,面積也逐漸增大,要降低成本就需縮小晶片面積,所以必須縮小製程,從製程單位進入奈米之後,90、65、45…奈米,晶片製程的發展已逐漸遇上瓶頸,製程不斷的縮小,卻有許多問題拖慢了發展的腳步,如漏電流,造成晶片耗電量上升;製程縮小也使光罩的成本不停上升,因為光繞射的物理效應,製程變異也更加嚴重。二維晶片的種種問題,也使三維晶片的發展更加地受到重視。
但是三維晶片製造上,要維持良率,堆疊前晶粒必須經過KGD (Known-Good Die)測試,晶片上必須的時脈樹也必須考慮堆疊前的可測試性,但之前的方法須加入額外的硬體成本過於龐大,本篇提出利用模擬退火(Simulated annealing)的方法流程,提供三維時脈樹的堆疊前可測試性,並最佳化所需的硬體成本。


致谢 ii
摘要 iii
第1章 簡介 1
1.1 研究目標 1
第2章 三維晶片遭遇之問題與相關研究 4
2.1 三維晶片遭遇之問題 4
2.2 相關研究 6
第3章 背景知識 10
3.1 Zero-skew時脈樹產生方法 10
3.2 三維時脈樹做堆疊前測試所遇到之問題 13
第4章 方法與實作 16
4.1 研究動機 16
4.1.1 MMM-3D 18
4.1.2 Assign-Embedding-Layer 20
4.1.3 DME-3D 23
4.2 本方法流程 26
第5章 實驗數據 30
第6章 結論 41
參考文獻 42



[1]G. E. Moore, “Cramming more components onto integrated circuits,” IEEE Trans. Electronics, vol. 38, no. 8, pp. 114–117, Apr. 1965
[2]R. Chau, S. Datta, M. Doczy, B. Doyle, J. Kavalieros, and M. Metz, “High-κ/metal-gate stack and its MOSFET characteristics,” IEEE Journal of Electron Device Letters, vol. 25, no. 6, pp. 408–410, Jun. 2004
[3]Varian Looks to Enforce Moore’s Law in Solar
http://www.greentechmedia.com/articles/read/varian-looks-to-enforce-moores-law-in-solar/
[4]P.-Y. Chen, C.-W. Wu, and D.-M. Kwai, “On-Chip Testing of Blind and Open-Sleeve TSVs for 3D IC before Bonding,” in Proc. VLSI Test Symp., pp. 263-268, 2010.
[5]P.-Y. Chen, C.-W. Wu, and D.-M. Kwai, “On-Chip TSV Testing for 3D IC before Bonding Using Sense Amplification,” in Proc. Asia Test Symp., pp. 450-455, 2009.
[6]J.-W. You, S.-Y. Huang, D.-M. Kwai, Y.-F. Chou, and C.-W. Wu, “Performance Characterization of TSV in 3D IC via Sensitivity Analysis,” in Proc. Asia Test Symp., pp. 389-394, 2010.
[7]J.-S. Yang, K. Athikulwongse, Y.-J. Lee, S.-K. Lim, and D. Z. Pan, “TSV Stress Aware Timing Analysis with Applications to 3D-IC Layout Optimization,” in Proc. Des. Autom. Conf., pp. 803-806, 2010.
[8]M. Mondal, A. J. Ricketts, S. Kirolos, T. Ragheb, G. Link, N. Vijaykrishnan, and Y. Massoud, “Thermally Robust Clocking Schemes for 3D Integrated Circuits,” in Proc. Des. Autom. Test Eur., pp. 1206-1211, 2007.
[9]E. J. Marinissen, J. Verbree, and M. Konijnenburg, “A Structured and Scalable Test Access Architecture for TSV-Based 3D Stacked ICs,” in Proc. VLSI Test Symp., pp. 269-274, 2010.
[10]C.-W. Chou, J.-F. Li, J.-J. Chen, D.-M. Kwai, Y.-F. Chou, and C.-W. Wu, “A Test Integration Methodology for 3D Integrated Circuits,” in Proc. Asia Test Symp., pp. 377-382, 2010.
[11]J. Li, X. Qiang, K. Chakrabarty, and T. M. Mak, “Layout-Driven Test-Architecture Design and Optimization for 3D SoCs under Pre-Bond Test-Pin-Count Constraint,” in Proc. Int. Conf. Comput.-Aided Des., pp. 191-196, 2009.
[12]J. Minz, X. Zhao, and S.-K. Lim, “Buffered Clock Tree Synthesis for 3D ICs Under Thermal Variations,” in Proc. Asia South Pacific Des. Autom. Conf., pp. 504-509, 2008.
[13]T.-Y. Kim and T. Kim, “Clock Tree Embedding for 3D ICs,” in Proc. Asia South Pacific Des. Autom. Conf., pp. 486-491, 2010.
[14]K.D. Boese, and A.B. Kahng, “Zero-skew Clock Routing Trees with Minimum Wirelength,” in Proc. ASIC Conf. and Exhibit, pp. 17-21,1992.
[15]X. Zhao, D. L. Lewis, H.-H. S. Lee, and S.-K. Lim, “Pre-bond Testable Low-Power Clock Tree Design for 3D Stacked ICs,” in Proc. Int. Conf. Comput.-Aided Des., pp. 184-190, 2009.
[16]T.-Y. Kim and T. Kim, “Clock Tree Synthesis with Pre-bond Testability for 3D Stacked IC Designs,” in Proc. Des. Autom. Conf., pp. 723-728, 2010.
[17]X. Zhao and S.-K. Lim, “Power and Slew-aware Clock Network Design for Through-Silicon-Via (TSV) based 3D ICs,” in Proc. Asia South Pacific Des. Autom. Conf., pp. 175-180, 2010.
[18]M.A.B. Jackson, A. Srinivasan, and E.S. Kuh, “Clock Routing for High-performance ICs, ” in Proc. Des. Autom. Conf., pp. 573-579, 1990.
[19]BST-DME. http://vlsicad.ucsd.edu/GSRC/bookshelf/Slots/BST/
[20]L.W. Nagel, and D. O. Pederson, “SPICE (Simulation Program with Integrated Circuit Emphasis),” Memorandum No. ERL-M382, University of California, Berkeley, 1973.
[21]Predictive Technology Model. http://www.eas.asu.edu/~ptm/


QRCODE
 
 
 
 
 
                                                                                                                                                                                                                                                                                                                                                                                                               
第一頁 上一頁 下一頁 最後一頁 top