臺灣博碩士論文加值系統

本論文探討應用於無線區域網路802.11a、24GHz、60GHz三種頻段的無線射頻接收器的射頻積體電路設計以及系統整合概念。內容包含電路設計、系統分析、晶片量測、結果與討論。論文整體主軸可分為四大部分：第二章為混波器原理介紹、第三章為應用於無線區域網路802.11a規格的混波器、第四章為應用於24GHz系統之混波器以及射頻前端電路及第五章的應用於60GHz系統之混波器。以下再就各章內容作概要說明：
第二章為混波器原理介紹，討論混波器的基本概念，及混波器常見的傳統基本架構介紹、各項效能參數討論。
第三章為應用於無線區域網路802.11a的混波器的研究。在此章中我們利用電流注入以及切換偏壓技巧設計一個超低雜訊的混波器。此電路使用台積電0.18μm CMOS製程製作。量測將5.2GHz射頻訊號直接降頻至50MHz後，測得之轉換增益為4.785dB，P1dB為-13dBm，雜訊指數為7.155dB。此電路於1.8V偏壓下的直流功率消耗為9.72mW。
第四章為應用於24GHz之混波器以及射頻前端電路設計。兩顆晶片亦皆為使用台積電0.18μm CMOS製程製作。第一顆電路利用改良過後的電流注入，設計一個24GHz直接降頻至50MHz的混波器。量測結果所得之轉換增益為8.2dB，P1dB為-8.4dBm，雜訊指數為11.6dB。此電路於1.8V偏壓下的直流功率消耗為5.544mW，並且設計在功率轉換增益與線性度近乎平衡的狀態。此章第二顆電路為一應用於24GHz由低雜訊放大器及混波器組成之射頻前端電路。在低雜訊放大器部份，我們利用電阻回授以及改善線性度等技巧，再結合原先已量測的混波器以實現完整的接收機電路。模擬所得的總電路之轉換增益為23.674dB，P1dB為-23.9dBm，雜訊指數為5.2dB，1.8V偏壓下的直流功率消耗為33.948mW。
第五章的內容則為應用於60GHz系統之混波器。使用台積電90nm CMOS製程製作。電路為利用平方律之架構，我們成功設計出一個將60GHz射頻訊號降頻至12GHz的混波器。量測結果此電路之轉換增益為4.567dB，P1dB為-4dBm，雜訊指數為14.925dB。此電路於1.2V偏壓下的直流功率消耗為3.7mW。

This thesis presents the receiver RFIC design for three band applications: WLAN 802.11a, 24GHz, and 60GHz, including circuit design and system conception. It is composed of four main parts: mixer design theorem, mixer design for WLAN 802.11a application, mixer and the receiver front end design for 24GHz application, and mixer design for 60GHz application. In each part, the content includes the circuit design, system analysis, chip measurement results, and a short discussion.
In chapter two, we introduce design theorem for mixers, and we discuss general considerations in the design of mixers. Furthermore, we describe conventional mixer topologies and performance parameters for mixers.
In chapter three, an ultra low noise mixer design by using current bleeding and switching bias technique for WLAN 802.11a application is presented. The circuit is implemented in the TSMC 0.18μm CMOS process technology. We operate the direct down conversion mixer for the RF being 5.2GHz and the IF being 50MHz. The measured power conversion gain is 4.785dB, P1dB is -13dBm, and noise figure is 7.155dB. The power consumption of the proposed mixer is 9.72mW under 1.8V supply voltage.
In chapter four, a mixer design and a receiver front end design for 24GHz applications are presented. Both designs are implemented in TSMC 0.18μm CMOS process technology. The first mixer directly down-converts the RF signal from 24GHz to IF 50MHz band using the improved current bleeding technology. The measurement results: show that the power conversion gain is 8.2dB, P1dB is -8.4dBm, and the noise figure is 11.6dB. The proposed mixer consumes 5.544mW dc power from the 1.8-V supply. The measured data show good balance between linearity and power conversion gain. The second circuit in this chapter is composed of a low noise amplifier and a mixer for 24GHz applications, in which the LNA uses resistive feedback and linearity improvement technology and the first circuit in this chapter is adopted as well. The simulation results show that the power conversion gain is 23.674dB, P1dB is -23.9dBm, and the noise figure is 5.2dB. The power consumption of the proposed receiver front end is 33.948mW under a 1.8V supply voltage.
In chapter five, the mixer design for 60GHz application which is implemented in TSMC 90nm CMOS process technology is presented. The proposed mixer down-converts the RF signal from 60GHz to 12GHz IF band using the square-law topology. The measurement results show that the power conversion gain is 4.567dB, P1dB is-4dBm, and the noise figure is 14.925dB. The power consumption of the proposed mixer is 3.7mW under 1.2V supply.

致謝 I
摘要 II
Abstract IV
目錄 VI
圖目錄 IX
表目錄 XII
第一章 緒論 1
1.1無線射頻系統背景 1
1.1.1無線射頻系統介紹 1
1.1.2 802.11a簡介 3
1.1.3 24GHz應用 3
1.1.4 60GHz應用 4
1.2論文大綱 5
第二章 混波器原理介紹 7
2.1混波器簡介 7
2.1.1 簡介 7
2.1.2 被動式混波器 8
2.1.3 單平衡主動混波器 9
2.1.4 雙平衡主動混波器 12
2.2混波器重要特性參數 17
2.2.1 轉換增益 17
2.2.2 線性度 18
2.2.3 雜訊指數 22
2.2.4 隔離度 24
第三章 應用於802.11a之混波器 25
3.1前言 25
3.2混波器電路分析與設計 25
3.2.1 電流注入技巧 25
3.2.2 切換偏壓技巧 28
3.2.3 電路架構 31
3.3應用於802.11a混波器電路佈局圖 34
3.4應用於802.11a混波器模擬與量測結果 36
3.4.1 電路模擬結果 36
3.4.2 量測考量 39
3.4.3 量測結果 40
3.5應用於802.11a混波器結果討論 46
第四章 應用於24GHz頻帶之混波器 及射頻前端電路 47
4.1前言 47
4.2應用於24GHz頻帶之混波器電路分析與設計 47
4.2.1 交叉耦合PMOS電流注入技巧 47
4.2.2 電路架構 51
4.3應用於24GHz頻帶之混波器電路佈局圖 53
4.4應用於24GHz頻帶之混波器模擬與量測結果 55
4.4.1 電路模擬結果 55
4.4.2 量測考量 59
4.4.3 量測結果 61
4.5應用於24GHz頻帶之射頻前端電路分析與設計 66
4.5.1 低雜訊放大器簡介 66
4.5.2 電感退化疊接低雜訊放大器 68
4.5.3 低雜訊放大器加入線性化技巧 71
4.5.4 電阻回授低雜訊放大器 73
4.5.5 電路架構 74
4.6應用於24GHz頻帶之射頻前端電路佈局圖 77
4.7應用於24GHz頻帶之射頻前端電路模擬結果 79
4.8應用於24GHz頻帶之混波器及射頻前端電路結果討論 84
第五章 應用於60GHz頻帶之混波器 85
5.1前言 85
5.2應用於60GHz頻帶之混波器電路分析與設計 86
5.2.1 系統架構 86
5.2.2 平方律混波器 87
5.2.3 電路架構 91
5.3應用於60GHz頻帶之混波器電路佈局圖 94
5.4應用於60GHz頻帶之混波器模擬與量測結果 96
5.4.1 電路模擬結果 96
5.4.2 量測考量 99
5.4.3 量測結果 100
5.5應用於60GHz頻帶之混波器結果討論 105
第六章 結論與未來展望 107
參考文獻 109

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