在積體系統晶片的發展上，嵌入式CMOS製程之非揮發性記憶體，可分為需要與不需要額外製程，前者較適合大容量記憶體，後者適合中小容量。本論文訴求以不需額外製程之標準0.18μm CMOS製程為主，提出嵌入式一次性寫入非揮發性記憶體與嵌入式可多次寫入非揮發性記憶體。在嵌入式一次性寫入非揮發性記憶體方面，針對以兩個N型金氧半場效應電晶體串聯所組成之ㄧ種簡單且記憶體元件面積小之嵌入式一次性寫入非揮發性記憶體的結構做研究，其操作模式因不同種類之記憶體元件而有所不同。
由於新製程的演進使氧化層之厚度持續減小，也造成一般儲存於浮動閘極中的載子容易流失，因此本論文另提出一相容於邏輯製程可多次寫入差動型非揮發性記憶體，此差動的優點是可以容許些微的漏電，且容易判別微小的電流差異，預期可能較適用於較新製程的嵌入式非揮發性記憶體。利用熱電洞注入完成寫入操作與熱電子注入完成抹除操作，其優點是操作電壓可以降低。當記憶體結構中的其中一邊浮動閘極被寫入後，導致浮動閘極0 (FG0)之電晶體和浮動閘極1 (FG1)之電晶體臨界電壓值的差異，使用感測放大器同時讀取浮動閘極0電晶體和浮動閘極1電晶體的通道電流值，產生一邏輯狀態輸出。

In the development of integrated system-on-chip, the CMOS embedded non-volatile memories can be categorized into with- and without- additional processes. The former is more suitable for large-capacity memories, while the latter is suitable for small- and medium-capacity memories. This thesis proposes embedded one-time programmable (OTP) non-volatile memory cells and embedded multiple-time programmable (MTP) non-volatile memory cells, which were fabricated by the standard 0.18μm CMOS technology without additional processes. For the OTP memories, a simple and small cell-size embedded OTP structure containing two N-type Metal-Oxide-Semiconductor Field Effect Transistors in series were investigated. The operation methods were varied for different types of transistors.
As the evolution of new processes continues to reduce the thickness of the gate oxide layers, the charges stored in the floating gate may be leaked faster. Therefore, this thesis also proposes a logic-compatible MTP differential non-volatile memory cell, which contains two floating gates in one cell. The advantage of the differential structure is allowing a slight leakage of the stored charges and easier to distinguish the small current difference. It is expected to be scalable for the advanced processes. Since hot-hole injection is used for program and hot-electron injection is applied for erase, the operating voltages can be reduced. When one floating gate is programmed, the threshold voltages of the floating gate 0 (FG0) transistor and the floating gate 1 (FG1) transistor are different. The sensing amplifier reads the channel currents of FG0 and FG1 transistors at the same time to determine a logic output.

誌謝.......................................................i
摘要......................................................ii
Abstract.................................................iii
目次......................................................iv
表目次....................................................vi
圖目次...................................................vii
第一章 序論...............................................1
1.1非揮發性記憶體之簡介...................................1
1.2浮動閘極非揮發性記憶體元件技術之發展...................2
1.3研究動機...............................................3
1.4論文大綱...............................................4
第二章 嵌入式非揮發性記憶體元件之技術回顧.................8
2.1非揮發性記憶體操作的物理機制...........................8
2.1.1通道熱載子注入機制..................................8
2.1.2汲極累增崩潰產生熱載子注入機制......................8
2.1.3福樂-諾德漢穿隧效應.................................8
2.1.4帶對帶穿隧效應產生熱載子注入機制....................9
2.1.5碰穿效應產生熱載子注入機制..........................9
2.2矽化物複晶矽熔絲記憶體................................10
2.3單層複晶矽可電性寫入非揮發性記憶體....................10
2.4 XPM一次性寫入非揮發性記憶體..........................10
2.5可多次寫入差動型非揮發性記憶體........................11
第三章 嵌入式一次性寫入非揮發性記憶體元件................19
3.1元件結構..............................................19
3.2寫入操作原理..........................................19
3.3讀取操作原理..........................................20
3.4元件量測系統架構......................................21
3.5元件基本特性分析：1.8V Native NMOS Type OTP...........21
3.5.1初始特性分析.......................................21
3.5.2寫入特性分析.......................................22
3.6元件基本特性分析：3.3V Native NMOS Type OTP...........22
3.6.1初始特性分析.......................................22
3.6.2寫入特性分析.......................................22
3.7元件基本特性分析：3.3V Normal NMOS Type OTP...........23
3.7.1初始特性分析.......................................23
3.7.2寫入特性分析.......................................23
3.8相關技術之比較........................................24
第四章 嵌入式可多次寫入差動型非揮發性記憶體元件..........35
4.1元件結構..............................................35
4.2寫入操作原理..........................................35
4.3抹除操作原理..........................................36
4.4讀取操作原理..........................................36
4.5元件基本特性分析：操作模式(一)........................37
4.5.1初始特性分析.......................................37
4.5.2寫入邏輯0特性分析..................................37
4.5.3抹除邏輯0特性分析..................................38
4.5.4寫入邏輯1特性分析..................................38
4.5.5抹除邏輯1特性分析..................................39
4.6元件基本特性分析：操作模式(二)........................39
4.6.1初始特性分析.......................................40
4.6.2寫入邏輯0特性分析..................................40
4.6.3抹除邏輯0特性分析..................................40
4.6.4寫入邏輯1特性分析..................................41
4.6.5抹除邏輯1特性分析..................................42
4.7相關技術之比較........................................43
第五章 總結..............................................62
參考文獻..................................................64

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