(54.236.58.220) 您好!臺灣時間:2021/03/06 22:31
字體大小: 字級放大   字級縮小   預設字形  
回查詢結果

詳目顯示:::

我願授權國圖
: 
twitterline
研究生:李佳峰
研究生(外文):Chia-Feng Li
論文名稱:半導體材料與元件的應變效應研究
論文名稱(外文):A Study for Effect of Strain on Semiconductor Materials and Devices
指導教授:張書通
口試委員:裴靜偉李昌駿
口試日期:2011-05-30
學位類別:碩士
校院名稱:國立中興大學
系所名稱:電機工程學系所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2011
畢業學年度:99
語文別:中文
論文頁數:65
中文關鍵詞:半導體場效電晶體薄膜電晶體應力應變
外文關鍵詞:semiconductorMOSFETTFTstressstrain
相關次數:
  • 被引用被引用:0
  • 點閱點閱:229
  • 評分評分:系統版面圖檔系統版面圖檔系統版面圖檔系統版面圖檔系統版面圖檔
  • 下載下載:0
  • 收藏至我的研究室書目清單書目收藏:0
本論文分為三個部份,第一部份使用新思科技公司(Synopsys) TCAD-Sentaurus Sband模擬工具研究施加應變在(001)表面且通道方向為[110]之NMOS元件上,對其遷移率的影響。第二部份使用ANSYS模擬軟體探討三種TFT結構,分別為下閘極、雙閘極與上閘極在機械彎曲下,不同撓曲曲率、閘極長度、楊氏係數與材料內部應力係數的應力分析。第三部份探討不同幾何結構對應變InGaAs NMOSFET元件之應力分布與遷移率的影響。

This paper was divided into three parts. With the simulation tool from Synopsys TCAD-Sentaurus Sband, part one studied impact of strain on electron mobility of NMOS with surface orientation of (001) and channel direction of [110]. With ANSYS simulation tool, part two analyzed stress distribution of three type of TFT structure devices, namely bottom gate, double gate and top gate, considering the effects of mechanical bending, gate length Young’s modulus and intrinsic stress in materials. Part three investigated strain impact of geometry structure on electron mobility, InGaAs NMOS using stress simulation tool ANSYS and Kubo-Greenwood mobility formula.

誌謝辭 i
中文摘要 ii
Abstract iii
目錄 iv
表目錄 vi
圖目錄 vii
第一章 簡介 1
1-1 研究架構 1
1-2 奈米級MOSFET背景 1
1-3 可繞式TFT背景 3
1-4 III-V元件介紹 4
第二章 ANSYS介紹 6
2-1 ANSYS軟體模組簡介 6
2-2 ANSYS分析之基本架構 7
2-2-2 求解器 10
2-2-3 後處理器 11
2-3 有限元素分析之基本原理 11
第三章 Sentaurus—Sband介紹 15
3-1 Sband 功能與模型介紹 15
3-1-1 元件結構(Device Structure) 15
3-1-2 次能帶計算(Calculating Subbands) 17
3-1-3 計算遷移率(Calculating Mobility) 22
3-2 應變對能帶之影響 22
3-3 應變對遷移率之影響 26
第四章 TFT撓曲與模擬 32
4-1 非晶矽(amorphous-Silicon,a-Si)電晶體 32
4-2 撓曲曲率變化 35
4-3 TFT尺寸相關性 40
4-4 楊氏係數 43
4-5 材料內部應力(intrinsic stress) 46
4-6 實際電子書/電子紙應力狀態(疊上EPD) 47
第五章 InGaAs NMOSFET模擬 51
5-1 III-V材料相關研究介紹 51
5-2 應力模擬 52
5-3 能帶結構運算 54
5-4 遷移率計算 57
第六章 結論與未來展望 61
參考文獻 62



[ 1 ] 半導體產業推動辦公室專刊NO.27,pp. 22,2007。
[ 2 ] 林宏年、呂嘉裕、林鴻志、黃調元,「局部與全面形變矽通道(strained Si channel)互補式金氧半(CMOS)之材料、製程與元件特性分析(I)」,奈米通訊第十二卷第一期,pp. 44-45,民國94年2月。
[ 3 ] C. Gallon, G. Reimbold, G. Ghibaudo, R.A. Bianchi, R. Gwoziecki, “Electrical analysis of external mechanical stress effects in short channel MOSFETs on (0 0 1) silicon,” Solid-State Electronics, vol. 48, pp. 561-566, 2004.
[ 4 ] 「可撓性顯示器用奈米類玻璃基板之研究」,政院國家科學委員會補助專題研究計畫成果報告,民國96年10月。
http://www2.che.nthu.edu.tw/nsc_polymer/nsc-polymer/95-report/PDF/952221E167015.pdf
[ 5 ] 中山科學研究院赴日本參加國際平面顯示器大展及技術研討會報告,pp.
17,2008。
http://open.nat.gov.tw/OpenFront/report_download.jspx?sysId=C09703686
[ 6 ] http://www.auo.com/?sn=54&lang=zh-TW。
[ 7 ] R. Chau, J. Brask, S. Datta, G. Dewey, M. Doczy, B. Doyle, J. Kavalieros, B. Jin, M. Metz, A. Majumdar, and M. Radosavljevic, “Application of High- k Gate Dielectrics and Metal Gate Electrodes to enable Silicon and Non-Silicon Logic Nanotechnology,” Microelectronic Engineering, vol. 80, pp. 1-6, 2005.
[ 8 ] M. K. Hudait, G. Dewey, S. Datta, J. M. Fastenau, J. Kavalieros, W. K. Liu, D. Lubyshev, R. Pillarisetty, W. Rachmady, M. Radosavljevic, T. Rakshit and R. Chau, “Heterogeneous Integration of Enhancement Mode In0.7Ga0.3As Quantum Well Transistor on Silicon Substrate using Thin (< 2 μm) Composite Buffer Architecture for High-Speed and Low-voltage ( 0.5V) Logic Applications,” International Electron Devices Meeting, Tech Dig., pp. 625-28, 2007.
[ 9 ] S. Suthram, P. Majhi, G. Sun, P. Kalra, H. R. Harris, K. J. Choi, D. Heh, J. Oh, D. Kelly, R. Choi, B.J. Cho, M. M. Hussain, C. Smith, S. Banerjee, W. Tsai, S. E. Thompson, H. H. Tseng, R. Jammy , “High Performance pMOSFETs Using Si/Si1-xGex/Si Quantum Wells with High-k/Metal Gate Stacks and Additive Uniaxial Strain for 22 nm Technology Node,” International Electron Devices Meeting Tech Dig., pp. 727-30, 2007.
[10] S. Suthram, Y. Sun, P. Majhi, I. Ok, H. Kim, H. R. Harris, N. Goel, S. Parthasarathy, A. Koehler, T. Acosta, T. Nishida, H. H. Tseng, W. Tsai, J. Lee, R. Jammy and S. E. Thompson, “Strain Additivity in III-V Channels for CMOSFETs beyond 22nm Technology Node,” Symposia on VLSI Tech Dig., pp. 182-83, 2008.
[11] H. C. Chin, X. Gong, X. Liu, Z. Lin, Y.C Yeo, “Strained In0.53Ga0.47As n-MOSFETs: Performance Boost with in-situ Doped Lattice-Mismatched Source/Drain Stressors and Interface Engineering,” Symposia on VLSI Tech Dig. pp. 244-45, 2009.
[12] 劉晉奇,電腦輔助工程分析入門:ANSYS速學,五南圖書出版股份有限公司,2009。
[13] 賴育良、林啟豪、謝忠祐,「ANSYS電腦輔助工程分析」,儒林圖書有限公司,台北,2001。
[14] 賴育良、林啟豪、謝忠祐,「ANSYS電腦輔助工程分析」,儒林圖書有限公司,台北,pp. 1-5~1-7,2002。
[15] 宋裕祺、蘇進國、張荻薇,「有限元素法在鋼斜張橋結構分析之應用」“Applications of Finite Element Method on Structural Analysis of Steel Cable-Stayed Bridges”,中日「鋼結構工程」研討會,Tainan, Taiwan,2007。
[16] 陳建良,國立中央大學機械工程研究所,「鐵路客車車廂結構體之應力與疲勞壽命分析」碩士論文,pp. 5,2000。
[17] Synopsys Sentaurus201003 user Manual.
[18] C. Droz, E. V.Sauvain, J. Bailat, L. Feitknecht, J. Meier, X. Niquille and A. Shah, “ELECTRICAL AND MICROSTRUCTURAL CHARACTERISATION OF MICROCRYSTALLINE SILICON LAYERS AND SOLAR CELLS,” Proceedings of 3rd World Conference on Photovoltaic Energy Conversion, Osaka. Japan, May 11-18, 2003.
[19] C. C. Lee, J. Huang, S. T. Chang and W. C. Wang, “Impact of channel width and dummy length on performance enhancement in p-type metal oxide semiconductor field effect transistor with a silicon-germanium alloy stressor,” Journal of Vacuum Science and Technology A, vol. 27, issue 3, pp. 1256, 2009.
[20] Sentaurus201003 SDEVICE manual.
[21] S. Suthram, J. C. Ziegert, T. Nishida, and S. E. Thompson, “Piezoresistance Coefficients of (100) Silicon nMOSFETs Measured at Low and High (~1.5 GPa) Channel Stress,” IEEE ELECTRON DEVICE LETTERS, vol. 28, pp. 58-61, 2007.
[22] S. Takagi, A. Toriumi, M. Iwase and H. Tango, “On the universality of inversion layer mobility in Si MOSFET''s: Part II-effects of surface orientation,” IEEE TRANSACTIONS ON ELECTRON DEVICES, vol. 41, pp. 2363-2368, 1994.
[23]Z. Xia, G. Du, X. Liu, J. Kang and R. Han, “Carrier effective mobilities in germanium MOSFET inversion layer investigated by Monte Carlo simulation,” Solid-State Electronics, vol. 49, pp. 1942-1946, 2005.
[24] Y. Zhang, M. V. Fischetti, B. Sorée, W. Magnus, M. Heyns, and M. Meuris, “Physical modeling of strain-dependent hole mobility in Ge p-channel inversion layers,” Journal Applied Physics, vol. 106, pp. 083704, 2009.
[25] 顧鴻壽、周本達、陳密、張德安、樊雨心、周宜衡,「平面面板顯示器基本概論二版」,全華圖書股份有限公司。
[26] 趙中興,「顯示器原理與技術」,全華圖書股份有限公司。
[27] 彩色軟性電子紙關鍵技術開發計畫(The key technology development of color flexible electronic paper),行政院國家科學委員會補助產學合作研究計畫成果精簡報告,2009。
http://test2.etop.org.tw/jspui/html/10537/17374/1253945935347.pdf
[28] ANSYS reference manual, 2007.
[29] 黃昌圳,「有限元素法在電機工程的應用」,全華科技出版,Ch.1。
[30] 陳信吉、張主聖,「Marc有限元素實例分析」,全華科技出版,Ch.2。
[31] http://www.matweb.com/index.aspx
[32] S. Wagner, H. Gleskova, I. Cheng, J. C. Strum and Z. Suo, “Mechanics of TFT Technology on Flexible Substrates, ” from Flexible Flat Panel Displays, John Wiley & Sons, Ltd., Chichester, G. P. Crawford, Editor, Chapter 14, 2005.
[33] Aneesh Nainani, Jung YumJoel Barnett, Richard Hill, Niti Goel, Jeff Huang, Prashant Majhi, Raj Jammy, and Krishna C. Krishna C. Saraswat, “Study of piezoresistance under unixial stress for technologically relevant III-V semiconductors using wafer bending experiments,” APPLIED PHYSICS LETTERS 96, 242110, 2010.
[34] ANSYS User manuals, 2006.
[35] H. C. Chin, X. Gong, X. Liu, and Y. C. Yeo, "Lattice mismatched In0.4Ga0.6As source/drain stressors with in situ doping for strained In0.53Ga0.47As channel n-MOSFETs," IEEE Electron Device Letters, vol. 30, no. 8, pp. 805-807, 2009.
[36] T. B. Boykin, G. Klimeck, R. C. Bowen, and F. Oyafuso, “Diagonal parameter shifts due to nearest-neighbor displacements in empirical tight-binding theory,” Phys. Rev. B, vol. 66, pp. 125207, 2002.
[37] C. C. Lee, S. T. Chang, P. H. Sun and C. X. Huang, “Impact of Strain Engineering on Nanoscale Strained InGaAs MOSFET Devices,” Nanoscience and Nanotechnology, Journal, vol. 11, pp. 1-5, 2010.
[38] M. V. Fischetti and S. E. Laux, Physical Review B, “Monte Carlo study of electron transport in silicon inversion layers,” vol. 48, pp. 2244-2274 ,1993.
[39] Y. Sun, S. E. Thompson, T. Nishida, “Strain Effect in Semiconductors: Theory and Device Applications,” Springer, pp. 178, 2010.
[40] T. O’Regan, M. Fischetti and J Comput, Electron, “Electron mobility in silicon and germanium inversion layers: The role of remote phonon scattering,” vol. 6, pp. 81-84, 2007.
[41] H. J. G. Meijer, Polder, Physica, “Extending continuous versus discontinuous conditioned stimuli before versus after unconditioned stimuli,” vol. 19, pp. 255-264, 1993.
[42] Yan Zhang, “Hole Mobility in Strained Ge and III-V P-channel Inversion Layers with Self-consistent Valence Subband Structure and High-k Insulators,” University of Massachusetts, Dissertations and Theses, 2010.


QRCODE
 
 
 
 
 
                                                                                                                                                                                                                                                                                                                                                                                                               
第一頁 上一頁 下一頁 最後一頁 top
系統版面圖檔 系統版面圖檔