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研究生:葉嘉豪
研究生(外文):Jia-Hao Ye
論文名稱:設計應用於CMOS技術之注入鎖定頻率除頻器
論文名稱(外文):Design of Injection-Locked Frequency Dividers in CMOS Technology
指導教授:許恒銘
口試委員:呂良鴻楊清淵
口試日期:2011-07-26
學位類別:碩士
校院名稱:國立中興大學
系所名稱:電機工程學系所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2011
畢業學年度:99
語文別:中文
論文頁數:92
中文關鍵詞:注入鎖定頻率除頻器
外文關鍵詞:Injection-Locked Frequency Dividers
相關次數:
  • 被引用被引用:3
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本論文分為三大主題,第一個主題為研究四相位壓控振盪器,先利用次諧波電路將振幅以及相位達到兩倍的輸出訊號的,再利用雙推式的原理將兩倍頻訊號組合成四倍頻訊號做回授,最後達到四相位的輸出。以TSMC 0.18um製成完成晶片製作,量測範圍為7.233 GHz至8.562 GHz,相位雜訊在1MHz的偏移量為-105.6dBc/Hz,功率消耗為1.65mW。
第二個主題為三種不同除率的注入鎖定除頻器設計,第一種為除二電路,利用轉導放大的技巧,以及並聯電晶體的差動雙注入方式,來增加注入訊號的轉導以及降低共振腔的品質因子,增加除頻器的鎖定範圍。以TSMC 0.18um製成完成晶片製作,量測的輸入頻率範圍為13.2 GHz至18.8 GHz,除頻範圍為35%,功率消耗為4mW。第二種為除三電路,使用注入鎖定除二除頻器以及雙平衡式的混頻器來完成除三的動作,其中電路均利用current bleeding的技巧,在除二電路上,可以使得注入的訊號增大藉以增加鎖定範圍;在混頻電路上,增加驅動級的轉導來推動下一級的電路,以減低下一級負載效應的影響,以TSMC 0.18um製成完成晶片製作,量測的輸入頻率範圍為19.6 GHz至24.5 GHz,除頻範圍為22.2%,功率消耗為14.2mW。第三種為四相位的除四電路,此電路主要是應用在24 GHz的射頻收發機架構上,將19 GHz的訊號除四之後,以4.75 GHz的四相位輸出給四相位的混頻器做混頻使用,以TSMC 0.18um製成完成晶片製作,量測的輸入頻率範圍為17 GHz至19.8GHz,除頻範圍為15.13%,功率消耗為14.2mW。
第三個主題為77 GHz的低雜訊放大器,利用共平面波導的傳輸線來做輸出入的匹配以及級間的匹配元件,此傳輸線使用ground shielding的技巧來減少訊號傳輸時對於基底的損耗,因為高頻電路的寄生效應會比一般低頻電路來的明顯,所以在加以探討電晶體的尺寸以及偏壓點的選擇,以達到最好的增益以及雜訊指數的表現,以TSMC 90nm製成完成晶片製作,模擬結果輸入以及輸出的反射係數均達到-10dB以下,增益S21為17.6dB,反向隔離度S12為-42dB,雜訊指數為6.1dB,其線性度之1dB之增益壓縮點為-17.7dBm,三階交調點為-7dBm左右,電路整體功率消耗為26.7mW。

目錄
致謝 I
中文摘要 II
Abstract IV
目錄 VI
圖目錄 IX
表目錄 XIII
第一章 序論
1-1前言 1
1-2文獻回顧 3
1-4論文架構 4
第二章 四相位壓控振盪器
2-1四相位壓控振盪器簡介 5
2-2電路架構 8
2-2-1完整電路架構 8
2-2-2雙推式技巧 9
2-2-3次諧波倍頻電路 11
2-2-4四相位的產生 12
2-3模擬與量測結果 15
2-3-1模擬與量測結果比較表 15
2-3-2電路佈局圖 20
2-3-3結果與討論 21
第三章 注入鎖定除二除頻器
3-1注入鎖定除二除頻器原理 23
3-2電路架構 30
3-2-1並聯電晶體差動雙注入技巧 30
3-2-2轉導提升技巧(Gm-boosting) 33
3-2-2電路完整架構 35
3-3模擬與量測結果 36
3-3-1模擬與量測結果比較表 36
3-3-2電路佈局圖 41
3-3-3結果與討論 42
第四章 注入鎖定除三除頻器與四相位除四除頻器
4-1除三除頻器原理 43
4-2注入鎖定除三除頻器電路架構 44
4-2-1完整電路架構 44
4-2-2注入鎖定除二除頻器 45
4-2-3雙平衡式混頻器 47
4-3模擬與量測結果 52
4-3-1模擬與量測結果比較表 52
4-3-2電路佈局圖 57
4-3-3結果與討論 58
4-4四相位除四除頻器在射頻收發機的應用 59
4-5四相位除四除頻器電路完整架構 60
4-6模擬與量測結果 61
4-6-1模擬與量測結果比較表 61
4-6-2電路佈局圖 67
4-6-3結果與討論 68
第五章 77GHz之低雜訊放大器
5-1低雜訊放大器基本特性 69
5-1-1放大器增益與穩定度 69
5-1-2放大器雜訊因子 71
5-1-3線性度 72
5-2電路架構 74
5-2-1完整電路架構 74
5-2-2共平面波導(Coplanar waveguide,CPW) 75
5-2-3設計考量 78
5-3模擬結果 80
5-3-1模擬與量測結果比較表 83
5-3-2電路佈局圖 84
5-3-3結果與討論 84
第六章 結論與未來工作目標
6-1結論 85
6-2未來工作目標 86
參考文獻
參考文獻 87


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