臺灣博碩士論文加值系統

在本篇論文中，利用乾蝕刻之非等向蝕刻特性，而不需要用先進昂貴的曝光設備來製作奈米通道，並利用濕蝕刻犧牲氧化層，讓多重奈米線通道懸空進而形成環繞式的閘極結構。最後再利用選擇性側向濕蝕刻，製作空腔長度為0.35微米以及0.7微米，在環繞式閘極邊緣靠近源極與汲極的上方蝕刻出空腔後，形成具有最低介電常數的真空閘極介電層。此外，利用乾蝕刻後的氮化矽側壁，經一次離子佈植後去形成輕汲極摻雜結構。簡單的製作出具有真空空腔和輕汲極摻雜架構的環繞式閘極多重奈米通道複晶矽薄膜電晶體，並擁有優越的特性。
當跟傳統平面式薄膜電晶體架構的元件比較時，環繞式閘極多重奈米通道薄膜電晶體具有較陡峭的次臨界擺幅由0.56V/dec降到0.42V/dec、較低的臨界電壓由2.7V降到2.06V、較大的開關電流比由0.861×107提升到3.8×107及較低的汲極引致能障下降由0.289V/V降到0.256V/V。當具有不同真空空腔長度為0.35微米以及0.7微米的環繞式閘極多重奈米通道膜薄電晶體比較時，臨界電壓雖然由2.06V增加到2.1V、2.48V，但漏電流在閘極負偏壓為-7V時，從7.38×10-9A降低到1.61×10-9A和5.24×10-9A且有較大的開關電流比由3.8×107增加到5.46×107、3.81×107 ，而在輕汲極摻雜結構的電晶體漏電流下降到1.05×10-9以及開關電流比上升到了4.71×107。
此外，進一步研究環繞式閘極多重奈米通道複晶矽薄膜電晶體，分別在熱載子效應及不同頻率的交流閘極偏壓應力下的可靠度。當跟傳統平面式薄膜電晶體的元件比較時，發現環繞式閘極多重奈米通道複晶矽薄膜電晶體，有較嚴重的衰退。當元件加入真空空腔架構以及輕汲極摻雜時，元件的可靠度分別在熱載子效應和交流閘極偏壓下都有明顯的改善，主要原因是真空空腔架構，具有較厚的等效閘極氧化層以及輕汲極摻雜可以有效降低靠近汲極端的橫向及垂直電場，進而提升元件的可靠度。

In this thesis, we utilize sidewall spacer technique to form multiple nanowire channels (MNCs) without any advanced lithography equipment. Furthermore, suspending multiple nanowire channels are formed by wet etching sacrificial SiO2 to establish the gate-all-around (GAA) structure. Finally, the vacuum cavity structure is formed by selective wet etching under the surrounding gate edges near source and drain. And then, the lowest permittivity material in nature (vacuum) is encapsulated into cavity by PECVD passvation. The lightly doped drain (LDD) structure is formed by the Si3N4 spacer near source and drain with one time ion implantation.Therefore, the GAA MNCs TFTs with the vacuum cavity and LDD structure are successfully fabricated , respectively and exhibit excellent electrical characteristics.
As compared with conventional planar TFTs, the proposed device has steeper subthreshold swing from0.56 V/dec to 0.42 V/dec、lower threshold voltage from2.7 V to2.06 V、higher ION/IOFF drain current ratio from0.86×107 to3.8×107 and smaller drain induce barrier lowing (DIBL) from 0.289 V/V to 0.256 V/V. GAA MNCs TFTs with different length vacuum cavity 0.35μm and 0.7μm, although slightly increased threshold voltage 2.1 V、2.48 V, respectively, but the leakage current at Gate voltage is -7 V, from 7.38×10-9 A reduces to 1.61×10-9 A and 5.24 × 10-9 A, respectively and a larger Ion / Ioff current ratio from 5.46×107 to upgrade to 3.81×107, and the GAA MNCs TFTs with LDD the leakage current reduces to 1.05 ×10-9A and the Ion / Ioff current ratio increases to 4.71×107.
In addition, we further study the reliability of GAA MNCs TFTs under hot carrier stress and dynamic gate bias stress with different frequency. the reliability of GAA MNCs TFTs degrade severely than that of planar TFTs due to the sharp corners.The reliability of GAA MNCs TFTs with vacuum cavity and LDD structures can be obviously improved after hot carrier stress or dynamic gate bias stress.The effective thicker gate insulator resulting from the vacuum cavity is the main reason to reduce both of the lateral and vertical electric field in the channel near drain region.

致謝 i
中文摘要 ii
Abstract iii
目次 iv
第一章 簡介 1
1.1概述複晶矽薄膜電晶體 1
1.2複晶矽的結晶方式 1
1.2.1 固相結晶法 2
1.2.2 準分子雷射結晶 2
1.2.3 金屬側向誘發結晶 2
1.3複晶矽薄膜電晶體的不良效應 3
1.3.1 漏電流 3
1.3.2 扭結效應 4
1.3.3 短通道效應 5
1.4複晶矽薄膜電晶體元件架構 5
1.5研究動機 6
1.6論文大綱 9
第二章 實驗步驟 10
2.1環繞式閘極多重奈米通道薄膜電晶體加入真空空腔製程 10
2.2 環繞式閘極多重奈米通道薄膜電晶體加入輕汲極摻雜製程 16
2.3 量測儀器介紹 17
2.4 電晶體各種電性參數萃取 18
2.4.1 轉導和載子遷移率定義 18
2.4.2 臨界電壓定義 18
2.4.3次臨界擺幅定義 19
2.4.4開關電流比定義 19
2.4.5 汲極偏壓導致通道電位能障降低定義 19
2.4.6 環繞式閘極多重奈米通道薄膜電晶體寬度計算 19
第三章 結果與討論 20
3.1真空空腔摻雜以及輕汲極摻雜結構對環繞式閘極多重奈米通道複晶矽薄 膜電晶體電性量測 20
3.2 短通道效應 27
3.3 閘極漏電流 33
3.4 熱載子應力可靠度測試 35
3.4.1 熱載子應力條件設計 36
3.4.2 熱載子應力測試實驗結果與討論 36
3.5 動態閘極偏壓應力測試 49
3.5.1 動態閘極偏壓應力測試條件設計 49
3.5.2 動態閘極偏壓應力測試結果與討論 51
第四章 結論 67
參考文獻 69

[1.1] Kaustav Banerjee, Shukri J. Souri, Pawan Kapur and Krishna C. Saraswat, “3-D ICs: A Novel Chip Design For Improving Deep-Submicrometer Interconnect Performance and System-on-Chip integration”, Proceedings of the IEEE, Vol. 89, no. 5, pp.602-633, May 2001.
[1.2] Bing-Yoe Tsui, Chia-Pin Lin, Chih-Feng Huang and Yi-Hsuan Xiao, “ 0.1μm Poly-Si Thin Film Transistors for System-on-Pannel (SOP) Applications ”, IEDM Tech. Dig. pp.911-914, December 2005.
[1.3] Toshiyuki Sameshima, Masaki Hara and Setsuo Usui, “ XeCl Excimer Leaser Annealing Used to Fabricate Poly-Si TFT’s ”, Japanese Journal of Applied Physics, Vol.28, no. 10, pp.1789-1793, October 1989.
[1.4] Akito Hara, Fumiyo Takeuchi, Michiko Takei, Katsuyuki Suga, Kenichi Yoshino, Mitsuru Chida, Yasuyuki Sano and Nobuo Sasaki, “High-Performance Polycrystalline Silicon Thin Film Transistors on Non-Alkali Glass Produced Using Continuous Wave Laser Lateral Crystallization”, Japanese Journal of Applied Physics, Vol.41, Part 2, no. 3B, pp.L311-L313, 15 March 2002.
[1.5] Chunya Wu, Zhiguo Meng, Xuedong Li, Shuyun Zhao, Zhaojun Liu, Juan Li, Shaozhen Xiong,Man Wong, and Hoi Sing Kwok” Metal induced crystallization of a-Si using a nano-layer of silicon oxide mask (MMIC)”, Phys. Status Solidi, C 7, No. 3–4, 608– 611 2010.
[1.6] K. R. Olasupo and M. K. Hatalis, “Leakage Current Mechanism in Sub-Micron Poly silicon Thin-Film Transistors” IEEE Transactions on Electron Devices, Vol. 43, no. 8, pp.1218-1223, August 1996.
[1.7] H. K. Jang, C. E. Lee, and S. J. Noh, “Poly-Si thin film transistors with a source overlap and a drain offset: Leakage current characteristics,” Thin Solid Films, Vol. 341, no. 1/2, pp. 148–151, Mar 1999.
[1.8] K. Tanaka, K. Nakazawa, S. Suyama, and K. Kato, “Characteristics of field-induced-drain (FID) poly-Si TFTs with high ON/OFF current ratio,” IEEE Transactions on Electron Devices, vol. 39, no. 4, pp.916–920, April 1992.
[1.9] C. M. Park, B. H. Min, J. H. Jun, J. S. Yoo, and M. K. Han, “Self-aligned offset gated poly-Si TFTs with a floating sub-gate,” IEEE Electron Device Letters., vol. 18, no. 1, pp.16–18, January 1997.
[1.10] J. I. Han and C. H. Han, “A self-aligned offset polysilicon thin-film transistor using photoresist reflow,” IEEE Electron Device Letters., vol. 20, no. 9,pp. 476–477, September 1999.
[1.11] B. H. Min, C. M. Park, and M. K. Han, “A novel offset gated polysilicon Thin film transistor without an additional offset mask,” IEEE Electron Device Letters, vol. 16, no. 5, pp.161–163, May 1995.
[1.12] Marina Valdinoci, Luigi Colalongo, Giorgio Baccarani, Guglielmo Fortunato, A. Pecora, and I. Policicchio, “Floating Body Effects in Polysilicon Thin-Film Transistors”, IEEE Transactions on Electron Devices, Vol. 44, no. 12, pp.2234-2241, December 1997.
[1.13] M. Hack and Alan G. Lewis, “Avalanche-Induced Effects in Poly silicon Thin-Film Transistors”, IEEE Electron Device Letters, Vol. 12, no. 5, pp.203-205, May 1991.
[1.14] Jong-Tae Park, and Jean-Pierre Colinge, “ Multiple-Gate SOI MOSFETs: Device Design Guidelines” IEEE Transactions on Electron Devices, Vol. 49, no. 12, pp.2222-2229, December 2002.
[1.15] Ali A.Orouji and M. Jagadesh Kumar, “ Leakage Current Reduction Techniques in Poly-Si TFTs for Active Matrix Liquid Crystal Display: A Comprehensive Study ”, IEEE Transactions on device and materials reliability, Vol. 6, no. 2, pp.315-325, June 2006.
[1.16] Shih-Ching Chen, Ting-Chang Chang, Po-Tsun Liu ,Y.C. Wu ,C.C. Tsai ,T.S. Chang, Chen-Hsin Lien, “High-performance polycrystalline silicon thin-film transistors with oxide–nitride–oxide gate dielectric and multiple nanowire channels” Thin Solid Films, Vol. 515, pp.1112-1116, 2006.
[1.17] Ta-Chuan Liao, Shih-Wei Tu, Ming H. Yu, Wei-Kai Lin, Cheng-Chin Liu, Kuo-Jui Chang, Ya-Hsiang Tai and Huang-Chung Cheng, “Novel Gate-All-Around Poly-Si TFTs With Multiple Nanowire Channels” IEEE Electron Device Letters, Vol. 29, no. 8, pp.889-891, August 2008.
[1.18] Min-Cheol Lee, Sang-Hoon Jung, In-Hyuk Song, and Min-Koo Han, “A New Poly-Si TFT Structure With Air Cavities at the Gate-Oxide Edges” IEEE Electron Device Letters, Vol. 22, no. 11, pp. 539-541, November 2001.
[1.19] Ta-Chuan Liao, Chun-Yu Wu,a Feng-Tso Chien, Chun-Chien Tsai, Hsiu-Hsin Chen, Chung-Yuan Kung, and Huang-Chung Cheng “A Poly-Si Thin-Film Transistor with the In Situ Vacuum Gaps under the T-Shaped-Gated Electrode” Electrochemical and Solid-State Letters, pp. G347-350, 2006.
[1.20] Po-Sheng SHIH, Ting-Chang CHANG,Tiao-Yuan HUANG,Ching-Fa YEH and Chun-Yen CHANG” Characterization and Reliability of Lightly-Doped-Drain Polysilicon Thin-Film Transistors with Oxide Sidewall Spacer Formed by One-Step Selective Liquid Phase Deposition” Jpn. J. Appl. Phys. 39, pp. 5758-5762, 2000
[3.1] Ji-Woon Yang and Jerry G. Fossum, “On the Feasibility of Nanoscale Triple-Gate CMOS Transistors”, IEEE Transaction on Electron Devices, Vol. 52, no. 6, pp.1159-1164, June 2005.
[3.2] Moselund KE, Bouvet D, Tschuor L, Pott V, Dainesi P, Ionescu AM. “Local volume inversion and corner effects in triangular gate-all-around MOSFETs”, Proceedings of European solid-state device research conference, pp. 359–362, 2006.
[3.3] Tsung-Kuei Kang, Chun-Kai Wang, I-Hsien Tsai, Ruei-Sheng Hung, , Yun-Feng Chenand Wen-Fa Wu. “Study PBTI and NBTI of GAA-MNC TFTs”,Microsystems Packaging Assembly and Circuits Technology Conference (IMPACT), 2010 5th International, pp. 978-1-4244-9783-6. 20-22 Oct. 2010
[3.4] Satoshi Inoue, Mutsumi Kimura and Tatsuya Shimoda, “Analysis and Classification of Degradation Phenomena in Polycrystalline-Silicon Thin Film Transistors Fabricated by a Low-Temperature Process Using Emission Light Microscopy”, Japanese Journal of Applied Physics, Vol. 42, pp.1168–1172, Part 1, No. 3, March 2003.
[3.5] Po-Chun Huang, Lu-An Chen, and Jeng-Tzong Sheu, “Electric-Field Enhancement of a Gate-All-Around Nanowire Thin-Film Transistor Memory”, IEEE Electron Device Letters, Vol. 31, no. 3,pp.216-218, March 2010.
[3.6] Ming-Shan Shieh, Jen-Yi Sang, Chih-Yang Chen, Shen-De Wang and Tan-Fu Lei “Electrical Characteristics and Reliability of Multi-channel Polycrystalline Silicon Thin-Film Transistors” Japanese Journal of Applied Physics, vol. 45, pp. 3159-3164, 2006.
[3.7] Yukiharu Uraoka, Hiroshi Yano, Tomoaki Hatayama and Takashi Fuyuki “Comprehensive Study on Reliability of Low-Temperature Poly-Si Thin-Film Transistors under Dynamic Complimentary Metal-Oxide Semiconductor Operations”, Japanese Journal of Applied Physics, Vol. 41 (2002) pp. 2414–2418, April 2002.
[3.8] Yukiharu Uraoka, Noboyuki Hirai, Hiroshi Yano, Tomoaki Hatayama, and Takashi Fuyuki, “Hot Carrier Analysis in Low-Temperature Poly-Si TFTs Using Picosecond Emission Microscope”, IEEE Transactions on Electron Devices, Vol. 51, no. 1,pp.28-34, January 2004.