臺灣博碩士論文加值系統

本篇論文主要研究方向為高速的傳輸介面，利用低電壓差動訊號傳輸技術來達到此目的，它包含傳輸器與接收器兩個部份。在傳輸器部分為了達到高速運作，利用交流耦合提供正回授路徑加快轉換的速度，並且利用電流控制電路節省多餘的電流消耗。在接收器方面為了有較大的共模電壓，採用互補式全差動對。此外，為了加快速度，比較器使用折疊疊接方式做設計。
實作方面以台積電提供的TSMC 0.18μm 1P6M CMOS製程進行設計與下線製作，傳輸器面積275μm × 140μm，接收器面積102μm × 96μm。在速度方面傳輸器與接收器可達到2G/bs，而傳輸器與接收器的功率消耗各為27mW與31mW。

This thesis presents a design of high-speed transmitter and receiver for low-voltage different signaling transmission interface. For achieving high-speed operation, an AC-coupled positive feedback path is added into the transmitter circuit for providing high-speed conversion. In addition a current-control circuit is employed to reduce the power dissipation. The receiver uses a complementary differential pair to get a wide range of common voltage. Furthermore, a folded-cascode type comparator is used for high speed operation.
A chip including the circuits of transmitter and receiver was implemented and verified by using TSMC 0.18-μm CMOS technology. The core area of the transmitter and receiver is 275μm × 140μm and 102μm × 96μm, respectively. The transmitter and receiver can operate at 2G/bs. The power consumption of the transmitter and receiver is 27mW and 31mW, respectively.

致謝 I
中文摘要 II
英文摘要 III
目錄 IV
圖目錄 V
表目錄 VII
第一章 緒論 1
1.1. 動機 1
1.2. 研究背景 1
1.3. 論文組織架構 2
第二章 低電壓差動訊號概論 3
2.1. 介紹 3
2.2. 規格 3
2.3. 低電壓差動訊號的基本電路架構 5
2.4. 低電壓差動訊號的優勢 8
2.5. 高速電路設計考量[2][3][4] 9
2.5.1. 反射(Reflect) 9
2.5.2. 串音(Crosstalk) 11
2.5.3. 接地彈跳(Ground Bounce) 12
2.5.4. 眼圖(Eye Diagram) 13
第三章 低電壓差動訊號電路設計 15
3.1. 傳輸器的分析 15
3.1.1. 傳輸器的原理 15
3.1.2. 傳輸器的電路設計 17
3.1.3. 傳輸器的模擬結果 23
3.2. 接收器的分析 26
3.2.1. 接收器的原理 26
3.2.2. 接收器的電路設計 27
3.2.3. 接收器的模擬結果 30
第四章 晶片佈局與量測 37
4.1. 電路佈局 37
4.2. 量測考量 43
4.3. 結果比較 44
第五章 結論 46
參考文獻 48

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