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研究生:鄭佳豪
研究生(外文):Cheng Chia-Hao
論文名稱:K-band及V-band晶片天線及相關電路之設計與實現
論文名稱(外文):Design and Implementation of K-band and V-band Chip Antenna and Related Circuit
指導教授:林佑昇林佑昇引用關係
口試委員:孫台平林佑昇梁效彬
口試日期:2011-06-15
學位類別:碩士
校院名稱:國立暨南國際大學
系所名稱:電機工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2011
畢業學年度:99
語文別:英文
論文頁數:94
中文關鍵詞:晶片天線陣列天線摺曲天線低雜訊放大器電流共用帶通濾波器
外文關鍵詞:chip antennaarray antennameander antennalow noise amplifiercurrent sharingbandpass filter
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  本篇論文主要以K頻帶與V 頻帶平面型CMOS天線、應用於超寬頻系統之帶通濾波器及K頻帶與V頻帶低雜訊放大器為研究目標,研究主題主要分成五個部分:
  第一部份是應用於V頻帶之寬頻CMOS晶片天線。利用陣列天線的架構來達到寬頻的需求。使用台積電0.18μm COMS製程實現此天線晶片。此天線晶片在47.5GHz–85.5GHz頻帶內,輸入返回損耗低於-10dB;頻寬為38.0GHz;60 GHz的頻率下天線增益為 -6.52dB;晶片總面積為1.33 mm2。
  第二部份是應用於24/60GHz之雙頻帶晶片天線。利用摺曲天線的架構來達到雙頻帶的需求。使用台積電0.18μm COMS製程實現此天線晶片。此天線晶片在13.5GHz–26.5GHz與40.5GHz–63.5GHz頻帶內,輸入返回損耗低於-10dB;頻寬分別為13.0GHz 與22.5GHz;24GHz與60GHz的頻率下天線增益分別為-21.8dB與-7.9dB;晶片總面積為1.1 mm2。
  第三部份是應用於超寬頻系統之低插入損耗帶通濾波器。使用台積電0.18μm COMS製程實現此濾波器。此濾波器在4.2GHz之插入損失為1dB;輸入返回損耗與輸出返回損耗頻寬範圍為2.4GHz–16.4GHz;晶片總面積為0.221 mm2。
  第四部份是K頻帶寬頻低雜訊放大器。使用台積電0.18μm COMS製程實現此低雜訊放大器。使用四個共源極放大器以獲得較大的增益,第二級與第三級採用電流共用技術降低電流消耗。此放大器的增益為13.39±1.47dB;輸入返回損耗在22.8GHz–50GHz頻帶內低於-10dB;輸出返回損耗在21GHz–27GHz頻帶內低於-8.65dB;雜訊指數為4.3-5.6dB;此電路消耗之功率為22.2 mW晶片總面積為0.72 mm2。
  最後,使用台積電0.09μm COMS製程設計應用於V頻帶寬頻低雜訊放大器。此低雜訊放大器為三級串接放大器架構,第一級使用一個共源極放大器,第二級與第三級都為共源極放大器與共閘極放大器之疊接組合。此放大器的增益為16.78±1.43dB;輸入返回損耗與輸出返回損耗在55GHz–65GHz頻帶內各低於-19.25與-14.56dB;雜訊指數為5.25-6.05dB;此電路消耗之功率為29.1 mW晶片總面積為29.1 mm2。

  The research focus of this present thesis is put on K-band and V-band CMOS antennas, UWB bandpass filter, and K-band and V-band low noise amplifiers. The research topics include the five parts, as listed below.
  The first part is about the application of V-band wide-band on-chip antenna. The configuration of array antenna was used to meet the need of wide-band. The antenna chip was designed by TSMC 0.18μm CMOS process. The frequency range of this on-chip antenna is within 47.5GHz–85.5GHz, S11 is below -10dB and the bandwidth is 38.0GHz. The maximum of antenna power gain at 60 GHz is -6.52dB, and chip size is 1.33 mm2.
  The second part is about the application of 24/60GHz dual-band on-chip antenna. The configuration of meander antenna was used to fit in the requirement of dual-band. The antenna chip was designed by TSMC 0.18μm CMOS process. The frequency range of the on-chip is within 13.5GHz–26.5GHz and 40.5GHz–63.0GHz, S11 is below 10dB and the bandwidth is 13.0GHz and 22.5GHz. The maximum of antenna power gain at -21.8dB and -7.9dB, and chip size is 1.1 mm2.
  The third part is about the UWB low insertion-loss bandpass filter. The filter chip was designed by TSMC 0.18μm CMOS process. As for filter, the insertion-loss is 1dB at 4.2GHz, the frequency range of S11 and S22 is 2.4GHz–16.4GHz, and chip size is 0.221 mm2.
  The fourth part is about the K-band low noise amplifier. The LNA chip was designed by TSMC 0.18μm CMOS process. In order to have an increasing gain, the four common-source amplifiers were used. The second and the third stage were adopted to current-sharing technology to lower power consumption. This LNA achieved gain is at 13.39±1.47dB. The frequency of S11 is within 22.8GHz–50GHz below -10dB. The frequency of S22 is within 21GHz–27GHz below -8.65dB;The noise figure is 4.3-5.6dB; the power consumption is 22.2mW, and chip size is 0.72 mm2.
  Last part is about the V-band wide-band low noise amplifier which was designed by TSMC 0.09μm CMOS process. The low noise amplifier is the configuration of the third stage cascade amplifier. The common-source amplifier was used in the first stage. The second and the third stage were the combination of common-source amplifier and common-gate amplifier. The power gain of this amplifier is 16.78±1.43dB, the frequency of S11 and S22 at 55GHz–65GHz are below -19.25 and -14.56dB, the noise figure is 5.25-6.05dB, the power consumption is 29.1 mW, and chip size is 0.66 mm2.

Chapter 1 Introduction 1
1-1. General Introduction 1
1-2. Thesis Organization 3
Chapter 2 A V-band Wide-band CMOS On-Chip Antenna 4
2-1. Introduction 4
2-1-1. Array Antenna 5
2-1-2. CPW (Coplanar Waveguide) 7
2-2. A V-band Wide-Band CMOS On-Chip Antenna design 10
2-3. Result and Discussion 12
Chapter 3 A 24/60 GHz Dual-Band On-Chip Meander Antenna 20
3-1. Introduction 20
3-1-1. Meander Antenna 20
3-2. A 24/60 GHz Dual-Band On-Chip Meander Antenna design 25
3-3. Result and Discussion 28
Chapter 4 A UWB Bandpass Filter 39
4-1. Introduction 39
4-1-1. Filter Design Theory [24] 39
4-2. Circuit Design 46
4-3. Simulation Results 49
4-4. Measurements Result 54
Chapter 5 A 21-27GHz Wide-Band LNA in 0.18μm CMOS
Technology 59
5-1. Introduction 59
5-2. Transmission Line Theory 61
5-3. Principle of The Circuit Design 62
5-4. Simulated Result 63
5-5. Measured Result 69
5-6. Conclusion 74
Chapter 6 A 55-65GHz Wide-Band LNA in 0.09μm CMOS
Technology 76
6-1. Introduction 76
6-2. Principle of The Circuit Design 77
6-3. Simulated Result 78
6-4. Conclusion 85

Chapter 7 Conclusions 87
References 89

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