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研究生:蔡永中
研究生(外文):Tsai, Yung-Chung
論文名稱:以FPGA實現在多載波分碼多工存取系統上的完全消除載波干擾技術
論文名稱(外文):Implementation of a Total ICI Cancellation Scheme for MC-CDMA System in FPGA
指導教授:許孟烈
指導教授(外文):Sheu, Meng-Lieh
口試委員:李彥文溫志宏
口試委員(外文):Lee, Yin-manWen, Jyh-Horng
口試日期:2011-07-05
學位類別:碩士
校院名稱:國立暨南國際大學
系所名稱:通訊工程研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2011
畢業學年度:99
語文別:中文
論文頁數:75
中文關鍵詞:多載波分碼多工存取載波間干擾可程式邏輯閘陣列
外文關鍵詞:MC-CDMAICIFPGA
相關次數:
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  • 下載下載:43
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在未來第四代行動通訊系統中,結合了正交分頻多工(OFDM)與分碼多工存取(CDMA)技術的多載波分碼多工存取系統(Multi-Carrier Code Division Multiple Access, MC-CDMA)是一個重要的候選存取技術。然而與OFDM相同地,MC-CDMA對於頻率偏移所造成的載波間干擾(Inter Carrier Interference, ICI)也非常敏感,系統效能很容易受到載波間干擾而大幅地降低。本論文利用可程式邏輯閘陣列(Field Programmable Gate Array, FPGA)發展板實現了兩個完全消除載波干擾的MC-CDMA傳收機架構,在此系統中使用QPSK作為調變技術,並加入展頻/解展頻電路,頻率偏移係數/解頻率偏移係數電路,判斷電路以及重複電路;在快速傅立葉轉換(Fast Fourier Transform, FFT)電路方面,使用Radix-2演算法以及Single-path Delay Feedback(SDF)的電路架構來實現;並且藉由MATLAB上的定點數模擬,進而在電路的面積以及資料的精確度上取得平衡,最後也比較了兩個架構之間的硬體複雜度。
Combining orthogonal frequency division multiplexing (OFDM) with code division multiple access (CDMA) technique, Multi-Carrier Code Division Multiple Access (MC-CDMA) is an important multiple access candidate for 4G mobile communication system in the future. However as same as OFDM, MC-CDMA is also highly sensitive to inter-carrier interference (ICI) resulted from carrier frequency offset (CFO). As a result, the system performance of MC-CDMA is easily reduced by ICI. In this thesis, we have implemented of two architectures for total ICI cancellation scheme in the MC-CDMA system with field programmable gate array (FPGA). The architectures include QPSK modulation, spreading/dispreading, CFO/deCFO coefficient, decision, and duplication circuits. Radix-2 algorithm and single-path delay feedback (SDF) are employed to implement the fast Fourier transform (FFT) circuit. The complexity of the hardware and the precision of data are balanced by performing a fixed-point simulation on MATLAB. Finally, a comparison is performed on hardware complexity of the two architectures.
目錄
中文摘要 .................................................Ⅰ
英文摘要 .................................................Ⅱ
目錄 ....................................................III
圖目錄 ....................................................V
表目錄 .................................................VIII
第一章 緒論 ...............................................1
1.1研究背景與動機..........................................1
1.2論文架構 ...............................................2
第二章 MC-CDMA系統與頻率偏移的影響.........................4
2.1多載波分碼多工存取系統(MC-CDMA)簡介.....................4
2.2MC-CDMA傳收機架構.......................................5
2.2.1傳送端................................................5
2.2.2接收端................................................7
2.3MC-CDMA接收端檢測方法...................................8
2.4MC-CDMA之載波頻率偏移(CFO)的影響.......................12
2.4.1子載波正交性與頻率偏移...............................12
2.4.2MC-CDMA受頻率偏移之數學分析..........................14
2.5MC-CDMA之ICI自我消除技術(ICI Self-Cancellation Scheme).19
2.6模擬結果...............................................21
第三章 載波干擾完全消除技術...............................26
3.1系統概述...............................................26
3.2數學分析...............................................26
3.2.1在AWGN通道的分析.....................................27
3.2.2在多路徑衰減通道(Multipath Fading Channels)的分析....30
3.3模擬結果...............................................32
第四章 系統之設計與模擬驗證...............................39
4.1實現系統架構介紹.......................................39
4.2系統電路設計...........................................40
4.2.1系統時脈(System Timing)電路設計......................40
4.2.2串並轉換(Serial-Parallel Converter)電路設計..........41
4.2.3QPSK映射(QPSK Mapping)電路設計.......................42
4.2.4快速傅立葉轉換(IFFT/FFT)電路設計.....................43
4.2.4.1Radix-2 DIF FFT演算法..............................43
4.2.4.2單一路徑延遲回授(SDF)..............................44
4.2.4.3Radix-2 SDF之電路架構..............................45
4.2.5展頻(Spreading)電路設計..............................46
4.2.6頻率偏移係數(Frequency Offset Coefficient)電路設計...47
4.2.7判斷(Decision)電路設計...............................48
4.2.8重複(Duplication)電路設計............................48
4.3系統之MATLAB電路模擬...................................49
4.4系統電路實現與驗證.....................................53
4.4.1FPGA發展板介紹.......................................53
4.4.2系統時脈電路實現.....................................54
4.4.3串並轉換電路實現.....................................55
4.4.4QPSK映射電路實現.....................................56
4.4.5展頻電路實現.........................................58
4.4.6快速傅立葉轉換電路實現...............................59
4.4.7頻率偏移係數電路實現.................................60
4.4.8判斷電路實現.........................................61
4.4.9重複電路實現.........................................62
4.5系統整合與硬體複雜度...................................63
4.5.1系統整合.............................................63
4.5.2硬體複雜度...........................................71
第五章
結論 .....................................................72
參考文獻 .................................................73

圖 目 錄
圖2.1MC-CDMA傳送端系統圖...................................5
圖2.2MC-CDMA訊號頻譜圖.....................................6
圖2.3MC-CDMA 接收端系統圖..................................7
圖2.4不同組合(Combing)之位元錯誤率(BER)效能圖.............12
圖2.5在頻域上無頻率偏移互相正交的子載波...................13
圖2.6在頻域上有頻率偏移失去正交的子載波...................13
圖2.7MC-CDMA傳送端架構....................................14
圖2.8經過頻率偏移後的MC-CDMA接收端架構....................14
圖2.9當SNR=20dB,QPSK星座圖...............................17
圖2.10不同頻率偏移下訊號的振幅衰減........................18
圖2.11不同頻率偏移下對訊號的相位旋轉......................18
圖2.12ICI自我消除之MC-CDMA系統架構........................19
圖2.13BPSK,頻率偏移為0.1時的錯誤率效能圖(AWGN)...........22
圖2.14QPSK,頻率偏移為0.1時的錯誤率效能圖(AWGN)...........22
圖2.15BPSK,頻率偏移為0.3時的錯誤率效能圖(AWGN)...........23
圖2.16QPSK,頻率偏移為0.3時的錯誤率效能圖(AWGN)...........23
圖2.17BPSK,頻率偏移為0.2時的錯誤率效能圖(頻率選擇性衰減通道) ...24
圖2.18QPSK,頻率偏移為0.2時的錯誤率效能圖(頻率選擇性衰減通道)....24
圖2.19BPSK,頻率偏移為0.3時的錯誤率效能圖(頻率選擇性衰減通道)....25
圖2.20QPSK,頻率偏移為0.3時的錯誤率效能圖(頻率選擇性衰減通道)....25
圖3.1不同的SNR下接收訊號差值與頻率偏移差值的比較圖........29
圖3.2接收端載波干擾完全消除技術的系統架構圖...............30
圖3.3當SNR=5dB,頻率偏移與錯誤率效能比較圖................31
圖3.4當SNR=20dB,完全消除載波干擾的QPSK星座圖.............32
圖3.5BPSK,頻率偏移為0.2854時的錯誤率效能圖(AWGN).........34
圖3.6QPSK,頻率偏移為0.1946時的錯誤率效能圖(AWGN).........34
圖3.7BPSK,頻率偏移為0.5174時的錯誤率效能圖(AWGN).........35
圖3.8QPSK,頻率偏移為0.6961時的錯誤率效能圖(AWGN).........35
圖3.9BPSK,頻率偏移為0.2038時的錯誤率效能圖(頻率選擇性衰減通道).....36
圖3.10QPSK,頻率偏移為0.091時的錯誤率效能圖(頻率選擇性衰減通道)........37
圖3.11BPSK,頻率偏移為0.6783時的錯誤率效能圖(頻率選擇性衰減通道).........37
圖3.12QPSK,頻率偏移為0.4136時的錯誤率效能圖(頻率選擇性衰減通道)......38
圖4.1完全消除載波干擾的MC-CDMA系統電路架構一..............39
圖4.2完全消除載波干擾的MC-CDMA系統電路架構二..............39
圖4.3(a)串並轉換電路 (b)並串轉換電路......................41
圖4.4QPSK星座映射圖.......................................42
圖4.5N = 8點的Radix-2 DIF FFT演算法運算流程圖.............44
圖4.6N = 8點的Radix-2 SDF電路架構圖.......................45
圖4.7(a) R2SDF工作模式1,(b)R2SDF工作模式2................45
圖4.8N = 8點的華氏哈達碼轉換運算流程圖....................46
圖4.9N = 8點的展頻(Spreading)電路架構圖...................46
圖4.10AWGN通道下,各種PSK之錯誤率對訊雜比曲線.............49
圖4.11輸入訊號位元數長度之定點數模擬環境..................50
圖4.12輸入位元長度對FFT輸出端之SNR曲線....................50
圖4.13IFFT位元數增減過程..................................51
圖4.14旋轉因子量化位元長度對 FFT輸出之SNR.................52
圖4.15旋轉因子量化成定點數之位元長度對FFT之SQNR...........53
圖4.16Spartan3 XC3S1500 CIC MorFPGA發展板.................54
圖4.17系統時脈區塊電路....................................54
圖4.18系統時脈電路時序波形模擬圖..........................54
圖4.19串並轉換與並串轉換的區塊電路........................55
圖4.20串並轉換電路和並串轉換電路的時序波形模擬圖..........55
圖4.21QPSK解映射電路的決策區間............................56
圖4.22QPSK映射與QPSK解映射的區塊電路......................57
圖4.23QPSK映射與QPSK解映射的時序波形模擬圖................57
圖4.24展頻電路與解展頻電路的區塊電路......................58
圖4.25展頻電路與解展頻電路的時序波形模擬圖................58
圖4.26IFFT與FFT的區塊電路.................................59
圖4.27IFFT與FFT電路的時序波形模擬圖.......................59
圖4.28頻率偏移係數與解頻率偏移係數的區塊電路..............60
圖4.29頻率偏移係數與解頻率偏移係數電路的時序波形模擬圖....61
圖4.30判斷電路的區塊設計..................................61
圖4.31判斷電路的時序波形模擬圖............................62
圖4.32重複電路的區塊設計..................................62
圖4.33重複電路的時序波形模擬圖............................62
圖4.34完全消除載波干擾架構一的區塊電路設計1/2(M = 4)......64
圖4.35完全消除載波干擾架構一的區塊電路設計2/2(M = 4) .....65
圖4.36完全消除載波干擾架構一之系統硬體消耗圖(M = 4).......65
圖4.37完全消除載波干擾架構一的時序波形模擬圖(M = 4).......66
圖4.38完全消除載波干擾架構二的區塊電路設計(M = 4).........67
圖4.39完全消除載波干擾架構二的時序波形模擬圖(M = 4).......68
圖4.40完全消除載波干擾架構二之系統硬體消耗圖(M = 4).......68
圖4.41完全消除載波干擾架構二經過AWGN的時序波形模擬圖(SNR =0dB,M =4) ....69
圖4.42完全消除載波干擾架構二經過AWGN的時序波形模擬圖(SNR = 4dB,M = 4)...69
圖4.43系統實現與系統模擬之位元錯誤率比較圖................70

表 目 錄
表2.1Multi-Carrier CDMA系統分類表..........................4
表2.2模擬參數一覽表.......................................21
表3.1模擬參數一覽表.......................................33
表3.2頻率偏移影響的錯誤率比較表(SNR = 8dB)................38
表4.1頻率偏移係數表.......................................47
表4.2頻率偏移定點數轉換表.................................47
表4.3QPSK Mapping的正規化與其9位元定點數..................56
表4.4完全消除載波干擾之MC-CDMA系統設計規格................63
表4.5硬體複雜度比較表.....................................71

[1]R. Chang, “Synthesis if band-limited orthogonal signals for multichannel data transmission,” BSTJ, vol. 46,
pp.1775-1796, December 1966.
[2]J. A. C. Bingham, “Multicarrier modulation for data transmission: an idea whose time has come,” IEEE
Communications Magazine, May 1990.
[3]J.G. Proakis, Digital Communications, 3rd Edition McGraw-Hill, 1995.
[4]A. J. Coulson, “Maximum likelihood synchronization for OFDM using a pilot symbol: analysis,” IEEE Journal on
Selected Areas in Communications, vol. 19, no. 12, pp. 2495-2503, 2001.
[5]Y. Yao and G. B. Giannakis, “Blind carrier frequency offset estimation in siso, mimo, and multiuser ofdm
systems,” IEEE Transactions on Communications, vol. 53, pp. 173-183, Jan. 2005.
[6]Y. Zhao and S. G. Häggman, “Intercarrier interference self-cancellation scheme for OFDM mobile communication
systems,” IEEE Transactions on Communications, vol. 49, no. 7, pp. 1185-1191, July 2001.
[7]Xue Li, Ruolin Zhou, Steven Hong, Zhiqiang Wu, “Total Inter-Carrier Interference Cancellation for MC-CDMA
System in Mobile Environment,” IEEE Global Telecommunications Conference, pp. 1-6, Dec. 2010.
[8]N. Yee, J-P Linnartz and G.Fettweis, “Multi-Carrier CDMA in Indoor Wireless Radio Networks”, IEEE PIMRC’93,
pp. 109-113, September 1993.
[9]Hara. S. and Prasad. R. “Overview of multicarrier CDMA” IEEE Communication Magazine,” pp. 126-133, Dec. 1997.
[10]Wu. Meng, ICI Reducation Methods for MC-CDMA Systems, M.S thesis, Dept. Elec. Eng., Information Technology
University, Beijing, China, 2008.
[11]Chin-Kuo Jao, Code Selection Methods for MC-CDMA Systems, M.S thesis, Dept. Elec. Eng., National Chi Nan
Univ., Puli, Taiwan, 2003.
[12]Ling-Yi Cheng, Implementation of a Novel Inter-Carrier Interference Suppression Scheme for OFDM System in
FPGA, M.S thesis, Dept. Com. Eng., National Chi Nan Univ., Puli, Taiwan , 2010.
[13]Xilinx. (2006, Jan. 11). Documentation [Online].
Available: http://www.xilinx.com/support/documentation/index.htm
[14]C. H Chang, FPGA Implementation of OFDMA Transceiver, M.S thesis, Dept. Elec. Eng., National Chi Nan Univ.,
Puli, Taiwan, 2009.
[15]S. He and M. Torkelson, “A new approach to pipeline FFT processor,” Proc. IPPS'96, pp. 766-770, Apr. 1996.
[16]S. He and M. Torkelson, “Design and implementation of a 1024-point pipeline FFT processor,” Proc. CICC'98,
pp. 131-134, Apr. 1998.
[17]S. He and M. Torkelson, “Designing pipeline FFT processor for OFDM (de)modulation,” Proc. ISSSE’98, pp. 257- 262, Oct. 1998.
[18]S. Sukhsawas and K. Benkrid, “A high-level implementation of a high performance pipeline FFT on Virtex-E
FPGAs,” Proc. ISVLSI'04, pp. 229-232, Feb. 2004.
[19]Sebastien Le Nours, Fabienne Nouvel, Jean-Franco, “Effcient Implementation of a MC-CDMA Transmission System
for the Downlink,” IEEE Vehicular tech. Conf., vol. 4, pp. 2-7, Fall, 2001.
[20]J. H. Reed, Software Radio: A Modern Approach to Radio Engineering, Upper Saddle River, NJ: Prentice-Hall,
2002.
[21]Phase Shift Keying. (2010, Jun. 8).[Online]:
Available: http://zh.wikipedia.org/zh-tw/PSK
[22]M. W. Chen, Wideband OFDM tranceiver realization with FPGA chip, M.S. thesis, Dept. Elec. Eng., National Chi
Nan Univ., Puli, Taiwan, 2008.
[23]J. L. Liu, Design of programmable FFT/IFFT in 802.16e system, M.S. thesis, Dept. Elec. Eng., National Chi Nan
Univ., Puli, Taiwan, 2005.
[24]Design Automation Standards Committee of the IEEE Computer Society, “IEEE Standard Hardware Description
Language Based on the Verilog® Hardware Description Language,” Dec.12, 1995.
[25]National Applied Research Lab. National Chip Implementation Center, MorFPGA Platform User Guide, Feb., 2008.

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