臺灣博碩士論文加值系統

在本論文中, 我們呈現了適用於IEEE 802.15.3c規格中四種碼率的低密度同位元檢查(LDPC)編解碼器。為了達到高解碼速度，我們使用了常態化最小和(normalized min-sum)演算法搭配排層流程(row-based layered scheduling)來降低迴圈數。此外，利用可重構8/16/32個輸入的排序器來處理四種碼率的解碼，並擁有幾乎可忽略的硬體代價。我們也提出排序器輸入的重置與繞線事先編排的網路來簡化繞線的複雜度。
編碼器方面，我們針對類循環(QC)-LDPC碼提出了一個更有效率的硬體電路來編碼。而我們實做了一個LDPC的編解碼器，其中也包括一個相加白高斯雜訊(AWGN)的通道。以65-nm CMOS製程實作，在1.1V供應電壓下，此晶片可達到最高5.69Gbps的解碼速度與有436.7mW的功率消耗。所提出的解碼器，在硬體與功率的效率都勝過其它解碼器。最後，我們也將提出的解碼器用在ADRES CGRA處理器來評估其效能。實驗結果指出這個具有16個功能運算單位(FU)的ADRES架構，可比傳統VLIW處理器有12.98倍的效能改善。

In this thesis, LDPC encoder and decoder designs supporting four code rates of IEEE 802.15.3c applications are presented. In order to achieve the throughput target, normalized min-sum algorithm with row-based layered scheduling is employed to reduce the iteration number. In addition, reconfigurable 8/16/32-input sorter is designed to deal with four code rates decoding with negligible hardware overhead. Both of the reallocation of sorter inputs and pre-coding routing switch are proposed to simplify the routing complexity.
For the LDPC encoder, an AASR circuit is proposed for QC-LDPC codes to encode codewords with efficient hardware. A LDPC codec including AWGN channel has been implemented. Fabricated in the 65 nm CMOS process, the chip can achieve maximum 5.69Gbps throughput with power of 436.7mW under 1.1V. The proposed LDPC decoder outperforms the others in the aspects of hardware efficiency and power efficiency. Finally, the proposed LDPC decoder is evaluated on the ADRES CGRA processor. Experiment results show that the ADRES architecture based on 16 FUs could outperform conventional VLIW processor by a factor of 12.98.

Chapter 1 Introduction 1
1.1 Overview of Forward Error Correction for High Data Rate Wireless Personal Area Network 1
1.2 Motivation 2
1.3 Thesis Organization 3
Chapter 2 LDPC Codes 4
2.1 Concept of LDPC 4
2.2 LDPC Codes for IEEE 802.15.3c Standard 6
Chapter 3 Algorithm Optimization for Implementation 8
3.1 LDPC Decoding Algorithm 8
3.1.1 Belief Propagation Algorithm 8
3.1.2 Normalized Min-sum Algorithm 11
3.1.3 Normalized Min-sum Algorithm with Row-based Layered Scheduling 13
3.1.4 Architecture Exploration 16
3.1.5 Performance Comparison 19
3.2 LDPC Encoding Scheme 25
Chapter 4 Architecture Design and Circuit Implementation 31
4.1 Decoder Design 31
4.1.1 Architecture Overview 31
4.1.2 Check Node Unit: Reconfigurable 8/16/32-input Sorter 33
4.1.3 Sorter Inputs Reallocation Switch 35
4.1.4 Pre-coding Routing Switch 38
4.1.5 Variable Node Group 41
4.1.6 Early Termination Block 43
4.2 Chip Implementation and Measurement Results 45
4.2.1 Chip Implementation 45
4.2.2 Measurement Setup and Results 47
Chapter 5 LDPC Decoder on the ADRES Coarse-Grained Reconfigurable Array Processor 53
5.1 Introduction to ADRES Processor 53
5.2 Architecture Description of ADRES Processor 54
5.3 Mapping Result of IEEE 802.15.3c LDPC Decoder 57
5.4 Conclusion 62
Chapter 6 Conclusion and Future Work 63
6.1 Conclusion 63
6.2 Future Work 64
Reference 65

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