在本論文中，我們成功地製作兩種新穎的元件結構，分別為具懸浮奈米線通道之薄膜電晶體(suspended-NW-channel TFTs)、與垂直式金氧半場效電晶體(VMOS)。其中，前者的懸浮奈米線通道、與後者的邊襯(sidewall spacer)閘極電極皆利用一簡單、低成本的反應式離子蝕刻(RIE)技術製作完成。此外，在後者的製作過程中，我們只使用兩個主要的微影光罩，以達到進一步降低成本的目的。
具懸浮奈米線通道之薄膜電晶體展現了極低的次臨界擺幅(subthreshold slope) (35 mV/dec.)、與相當大的遲滯窗口(hysteresis window) (3.7 V)。我們發現擺入(pull-in)汲極電流限制效應、汲極電流的似暫態行為、非對稱低次臨界擺幅與遲滯窗口打開的特性。除此之外，我們還發現，隨著幾何結構尺寸與閘極電壓掃描速率的改變，遲滯窗口、擺入電壓(Vpi)、擺出電壓(Vpo)、擺入之低次臨界擺幅(S.S.F)與擺出之次臨界擺幅(S.S.R)都有特定的變化趨勢。最後，依據以上所有的發現，我們提出一個觀念性的模型，用以描述元件操作時靜電力、彈性回復力與表面黏滯力之間的交互作用。
另一方面，當操作在順向操作模式時，垂直式金氧半場效電晶體展現了良好的開關電流比(106)與可接受的抗貫穿能力(anti-punch through ability)。此外，我們也發現一個有趣的兩段式開啟特性，並且解釋為凸邊角效應的結果。

In this thesis, we have successfully developed and fabricated two kinds of novel device structures, including suspended-nanowire (NW)-channel thin film transistors (TFTs) and vertical metal-oxide-semiconductor field-effect transistors (VMOS). The suspended NW channels in suspended-NW-channel TFTs and the sidewall spacer gate electrode in VMOS are formed by a simple and low-cost reactive ion etch (RIE) technique. Especially, in VMOS, further cost down could be achieved as only two main photolithographic reticles are needed through the process.
The suspended-NW-channel TFTs with ultra-low subthreshold swing (S.S.) (35 mV/dec.) and considerable hysteresis window (3.7 V) are demonstrated. The limited pull-in drain current (ID), the transient-like behavior in ID, the asymmetric S.S., and the hysteresis window opening characteristics are also observed. Besides, the specific trends in hysteresis window, Vpi, Vpo, S.S.F and S.S.R with the change of geometric structure dimensions and VG sweeping rate are found and analyzed. Finally, based on all of the above observations, a conceptual model illustrating the interaction between the electrostatic force, the elastic recovery force and the surface adhesion forces during device operation is proposed.
On the other hand, the VMOS devices exhibit a good on-off ratio of 106 and acceptable anti-punch through ability. In addition, an interesting two-step turn-on characteristic is also observed and explained by the convex corner effect.

Abstract (Chinese) i
Abstract (English) iii
Acknowledgment (Chinese) v
Contents vi
List of Figure Captions viii
List of Table Captions xiv

Chapter 1 Introduction 1
1-1 Overview of Vertical MOSFETs 1
1-2 Overview of Low Subthreshold-Swing Devices 3
1-2-1 Impact-ionization MOS (I-MOS) 4
1-2-2 Tunneling FET (T-FET) 6
1-2-3 Suspended-gate MOSFET (SG-MOSFET) 7
1-2-4 Suspended-NW-channel Device 9
1-3 Motivation 10
1-4 Organization of this Thesis 11

Chapter 2 Device Fabrication 12
2-1 Device Structure and Process Flow of Suspended-NW-Channel TFTs 12
2-2 Device Structure and Process Flow of Vertical MOSFETs 13
2-3 Measurement Setup and Electrical Characterization 16
Table Captions 18

Chapter 3 Electrical Characteristics of Suspended-NW-channel TFTs 19
3-1 Basic Electrical Characteristics 19
3-2 Hysteresis Phenomenon 20
3-2-1 Basic Hysteresis Characteristics 21
3-2-2 Effects of Structure Dimension 24
3-2-3 Effects of VG Sweeping Rate 27
3-2-4 Summary 28
3-3 Operation Mechanism 28
Table Captions 31

Chapter 4 Electrical Characteristics of Vertical MOSFETs 32
4-1 Background 32
4-2 Basic Electrical Characteristics 33
4-3 Discussion 35
Table Captions 37

Chapter 5 Conclusion and Future Work 38
5-1 Conclusion 38
5-2 Future Work 40

References 42
Figure Captions 46
Vita 87
Publication List 88

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