近年來，三維積體電路成為一個重要的趨勢，它帶來的好處有增加電路的效能和減少繞線長度，但是相對的也帶來很嚴重的熱度問題。在這篇論文裡，提出一個三維積體電路的熱相關功能區塊的放置位置演算法，藉由三維切割減少矽穿孔的數量以及藉由三維積體電路的功能區塊的放置位置來最佳化繞線長度與熱度。熱影響被結合在繞線的比例上，因此最小切割布局法可以考慮到熱。另外，我們用了空白空間來散熱。在實驗結果顯示，我們的三維積體電路的熱相關功能區塊的放置位置演算法可以減少29％的最高溫度只需要增加2%的繞線長度做為代價。

The 3D IC technologies can improve circuit performance and reduce wirelength. However, its thermal problems have become more serious. In this thesis, we propose a thermal aware 3D IC placement by using 3D partition to reduce the number of through-silicon via and to optimize wirelength and temperature. In our methods, thermal effect is integrated with the placement process by net weighting so that the min-cut in every partition process would reduce temperature. Furthermore, we distribute white space uniformly to dissipate heat. The experimental results show that our thermal aware 3D IC placement algorithm can reduce about 29% max temperature with only 2% increase on wirelength.

1 Introduction 1
1.1 Motivation and Contributions 1
1.2 Thesis Organization 3
2 Preliminaries 4
2.1 Thermal-Aware 3D IC Placement Overview 4
2.1.1 3D IC Placement 4
2.1.2 Temperature Calculation 5
2.2 Problem Formulation 6
3 Methodology 8
3.1 The Flow of Our Methodology 8
3.2 Layer Assignment Considering Area Balance 9
3.3 Thermal Model 11
3.3.1 Heat Transfer Equation 11
3.3.2 Finite Difference Method 12
3.4 Partitioning-Based Placement Considering White Space Distribution . 15
3.4.1 Thermal-Aware Net-Weighting 16
3.4.2 White Space Distribution 18
3.5 Simulated Annealing Re¯nement 19
4 Experimental Results 21
5 Conclusions and Future Works 24

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