在此篇文獻中，我們已經最佳化表面處理使得砷化鎵的表面費米能階可成功到達反轉區，也將砷化鎵能隙中間的Dit值降低至2E12cm-2V-1。首先，我們先探討利用原子層沉積氧化鋁做為閘極氧化層的電容電性，使用Berlund積分公式求出半導體表面費米能階與閘極電壓關係，並且比較不同Dit在砷化鎵能隙中分佈的萃取方式。其次，我們探討在沉積氧化鋁之前，利用三甲基鋁，還原基板表面的氧化物，其對砷化鎵電容特性的影響。雖然在電容的電性以及XPS分析上沒有發現明顯的改善，但是經過TEM照片的輔助，計算出閘極氧化層的介電值與等效氧化層厚度有明顯的改進。接著，我們探討不同表面晶向(100)與(111)A的基板的電容特性。發現利用基板晶向為(111)A的電容特性具有很大的改進，可以使表面費米能階成功到達反轉區，也將砷化鎵能隙中間的Dit值降低，我們推測改善是源自於基板表面結構不同所致。針對電容研究的情形，我們利用已經最佳化過後的表面處理去製作出砷化鎵場效應電晶體。
最後我們成功在半絕緣的基板上製作出原子層沉積氧化鋁高介電層之增強式砷化鎵N型場效電晶體。砷化鎵場效電晶體( 寬度/長度 = 100 μm/50 μm )的載子遷移率峰值為15 cm2V-1s-1，而電晶體( 寬度/長度 = 100 μm/5 μm )的電流開關比為4.12E3。雖然成功製作出電晶體，不過元件特性尚未預期的好，我們推測是由於電晶體的源極與汲極的活化步驟的條件沒掌控好所導致。此外，我們也成功製作出通道為砷化銦鎵而源極與汲極為磊晶鍺異質接面的金半場效電晶體，並探討其元件特性。

In this thesis, we demonstrated that the Fermi level (EF) of GaAs on the surface could be adjusted to the level of the inversion mode via optimizing the surface treatment. With the optimized treatment, the interface state density (Dit) in the middle of energy bandgap of GaAs could be significantly eliminated to a value of 2E12cm-2V-1. At first, we studied the electrical characteristics on GaAs MOS capacitor with Al2O3 gate dielectric formed by atomic-layer-deposition (ALD). We not only utilized Berglund’s integration to obtain the relation between surface potential and gate voltage but also compared the Dit distribution within energy bandgap by the different extraction methods. Next, we studied the reduction of native oxides on GaAs substrates by trimethylaluminum (TMA) pretreatment before ALD of Al2O3 and examined the impact of the electrical characteristics on GaAs MOS capacitors. Although we did not observe anything different on electrical characteristics and XPS analysis, we found the improvement in the value of k and effective oxide thickness after calculation with the TEM image. Then, we studied the electrical characteristics on GaAs MOS capacitors with the different surface orientation of substrates. There was improvement on GaAs MOS capacitors with (111)A surface orientation. The EF of surface on GaAs could reach inversion region and the value of Dit in the middle of energy bandgap was decreased. We presumed that improvement was caused by the different structure of surface on substrate.
Finally, we fabricated E-mode GaAs n-MOSFET on semi-insulator substrate. The electronic mobility we extracted was 15 cm2V-1S-1 and the on/off ratio was 4.12E3; the lower mobility and poor on/off ratio were due to the unsuccessful S/D activation. In addition, we also fabricated InGaAs channel MESFET with Ge S/D and studied electrical characteristics.

Contents
Abstract (Chinese) -------------------------------------- i
Abstract (English) ------------------------------------ iii
Acknowledgments ---------------------------------------- v
Contents ----------------------------------------------- vii
Table Captions ------------------------------------------- x
Figure Captions ---------------------------------------- xi

Chapter 1
Introduction
1.1 General Background ----------------------------- 1
1.2 Motivation ------------------------------------- 2
1.3 Organization of This Thesis -------------------- 3
References ---------------------------------------------- 4

Chapter 2
Electrical characteristics of GaAs MOS capacitor
with Al2O3 gate dielectric
2.1 Introduction ----------------------------------- 8
2.2 Sample Preparation ---------------------------- 11
2.3 Results and Discussion ------------------------ 12
2.3.1 Multi-Frequency C-V of GaAs MOS Capacitor ----- 12
2.3.2 Conductance Method Application of GaAs MOS
Capacitor ------------------------------------- 13
2.3.3 Comparison of Dit Extraction ------------------ 13
2.1 Summary --------------------------------------- 14
References --------------------------------------------- 15

Chapter 3
Optimization of Al2O3/GaAs interface with MOS capacitor
3.1 Introduction ---------------------------------- 24
3.2 Experimental Procedures ----------------------- 26
3.3 Results and Discussion ------------------------ 28
3.3.1 TMA Effect ------------------------------------ 28
3.3.2 PDA Effect ------------------------------------ 29
3.3.3 Surface Orientation Effect -------------------- 30
3.4 Summary --------------------------------------- 31
References --------------------------------------------- 33

Chapter 4
Fabrications of GaAs MOSFET and InGaAs MESFET
4.1 Introduction ---------------------------------- 47
4.2 Experimental Procedures ----------------------- 49
4.2.1 Device Structure ( MESFET ) ------------------- 49
4.2.2 Device Structure ( MESFET with Ge S/D ) ------- 49
4.2.3 Device Structure ( MOSFET ) ------------------- 50
4.3 Results and Discussion ------------------------ 51
4.3.1 Electrical Characteristics of InGaAs MESFET --- 51
4.3.2 Electrical Characteristics of Ge-S/D InGaAs ME
SFET ------------------------------------------ 52
4.3.3 Electrical Characteristics of E-mode GaAs n-
MOSFET ---------------------------------------- 53
4.4 Summary --------------------------------------- 54
References --------------------------------------------- 55

Chapter 5
Conclusion and Suggestions
5.1 Conclusion ------------------------------------ 69
5.2 Suggestions ----------------------------------- 70

Vita ( in Chinese ) ------------------------------------ 72

[1] D. Lin, G. Brammertz, S. Sioncke, C. Fleischmann, A. Delabie, K. Martens, H. Bender, T. Conard, W. H. Tseng, J. C. Lin, W. E. Wang, K. Temst, A. Vatomme, J. Mitard, M. Caymax, M. Meuris, M. Heyns, T. Hoffmann, “Enabling the high-performance InGaAs/Ge CMOS: a common gate stack solution,” Tech. Dig. Int. Electron Devices Meet., p. 327, 2009.
[2] J. Robertsona, B. Falabretti, “Band offsets of high K gate oxides on III-Vsemiconductor,” J. Appl. Phys., vol. 100, p. 014111, 2006.
[3] K. Iiyama, Y. Kita, Y. Ohta, M. Nasuno, S. Takamiya, K. Higashimine, and N. Ohtsuka, IEEE Trans. Electron Devices, vol. 49, p. 1856, 2002.
[4] J. K. Yang, M. G. Kang, and H. H. Park, J. Appl. Phys. vol. 96, p. 4811, 2004.
[5] P. D. Ye, G. D. Wilk, J. Kwo, B. Yang, H. J. L. Gossmann, M. Frei, S. N. G. Chu, J. P. Mannaerts, M. Sergent, M. Hong, K. K. Ng, and J. Bude, IEEE Electron Device Lett., vol. 24, p. 209, 2003.
[6] M. Xu, Y. Q. Wu, O. Koybasi, T. Shen, and P. D. Ye, “Metal-oxide-semiconductor field-effect transistors on GaAs (111)A surface with atomic-layer-deposited Al2O3 as gate dielectrics,” Appl. Phys. Lett., vol. 94, p. 212104, 2009.
[7] B. Yang, P. D. Ye, J. Kwo, M. R. Frei, H. J. L. Gossnann, J. P. Mannaerts, M. Sergent, M. Hong, K. Ng, and J. Bude, J. Cryst. Growth, vol. 251, p. 837, 2003.
[8] H.-L. Lu, L. Sun, S.-J. Ding, M. Xu, D. W. Zhang, and L.-K. Wang, “Characterization of atomic-layer-deposited Al2O3/GaAs interface improved by NH3 plasma pretreatment,” Appl. Phys. Lett., vol. 89, p. 152910, 2006.
[9] M. Zhu, C.-H. Tung, and Y.-C. Yeo, “Aluminum oxynitride interfacial passivation layer for high-permittivity gate dielectric stack on gallium arsenide,” Appl. Phys. Lett. vol. 89, p. 202903, 2006.
[10] M.-K. Lee, C.-F. Yen, J.-J. Huang, and S.-H. Lin, “Electrical characteristics of postmetallization-annealed MOCVD-TiO2 films on ammonium sulfide-treated GaAs,” J. Electrochem. Soc., vol. 153, p. F266, 2006.
[11] H.-S. Kim, I. Ok. M. Zhang, T. Lee, F. Zhu, L. Yu, and J. C. Lee, “Metal gate-HfO2 metal-oxide-semiconductor capacitors on n-GaAs substrate with silicon/germanium interfacial passivation layers,” Appl. Phys. Lett., vol. 89, p. 222903, 2006.
[12] C.G.B. Garrett and W.H. Brattain. Physical theory of semiconductor surfaces. Physical Review, vol. 99, p. 376-387, 1956.
[13] K. Lehovec. Frequency dependence of the impedance of distributed surface states in MOS structures. Appl. Phys. Lett., vol. 8, p. 48, 1966.
[14] E.H. Nicollian and A. Goetzberger. The Si/SiO2 interface - electrical properties as determined by the metal-insulator-silicon conductance technique. Bell Syst. Tech. J., vol. 46, p. 1055, December 1967.
[15] Nicollian and Brews. MOS (Metal Oxide Semiconductor) Physics and Technol-ogy., Wiley & Sons, New York, 1982.
[16] E.M. Vogel, W.K. Henson, C.A. Richter, and J.S. Suehle, “Limitation of Conductance to the Measurement of the Interface State Density of MOS Capacitors with Tunneling Gate Dielectrics,” IEEE Trans. Electron Dev., vol. 47, p. 601-608, March 2000; T.P. Ma and R.C.Barker, “Surface-State Spectra from Thick-oxide MOS Tunnel Junctions,” Solid-State Electron. vol. 17, p. 913-929, Sept. 1974.
[17] G. Brammertz, H. C. Lin, K. Martens, D. Mercier, C. Merckling, J. Penaud,c C. Adelmann, S. Sioncke, W. E. Wang, M. Caymax, M. Meuris, and M. Heyns, “Capacitance–Voltage characterization of GaAs–Oxide Interfaces,” Journal of The Electrochemical Society, vol.155, p. 945-950, 2008.
[18] C.N. Berglund, “Surface States at Steam-Grown Silicon-Silicon Dioxide Interfaces,” IEEE Trans. Electron Dev., vol. 13, p. 701-703, Oct. 1966.
[19] R. Castagne and A. Vapaille, “Description of the SiO2-Si Interface Properties by Means of Very Low Frequency MOS Capacitance Measurements,“ Surf. Sci., vol. 28, p. 157-193, Nov. 1971.
[20] E. Duval and E. Lheurette, “Characterization of Charge Trapping at the Si-SiO2 (100) Interface Using high temperature Conductance Spectroscopy,” Microelectron. Eng., vol.65, p. 103-112, Jan. 2003.
[21] C. L. Hinkle, A. M. Sonnet, E. M. Vogel, S. McDonnell, G. J. Hughes, M. Milojevic, B. Lee, F. S. Aguirre-Tostado, K. J. Choi, J. Kim, and R. M. Wallace, “Frequency Dispersion reduction and bond conversion on n-type GaAs by in situ surface oxide removal and passivation,” Appl. Phys. Lett., vol. 91, p. 183512, 2007.
[22] W. E. Spicer, N. Newman, C. J. Spindt, Z. Liliental‐Weber, and E. R. Weber, “Pinning and Fermi level movement at GaAs surfaces and interfaces,” J. Vac. Sci. Technol. A, vol. 8, p. 2084, 1990.
[23] M. Xu, Y. Q. Wu, O. Koybasi, T. Shen, and P. D. Ye, “Metal-oxide-semiconductor field-effect transistors on GaAs (111)A surface with atomic-layer-deposited Al2O3 as gate dielectrics,” Appl. Phys. Lett., vol. 94, p. 212104, 2009.
[24] Martin M. Frank, Glen D. Wilk, Dmitri Starodub, Torgny Gustafsson, Eric Garfunkel, Yves J. Chabal, John Grazul, and David A. Muller, “HfO2 and Al2O3 gate dielectrics on GaAs grown by atomic layer deposition,” Appl. Phys. Lett., vol. 86, p. 152904, 2005.
[25] C. L. Hinkle, A. M. Sonnet, E. M. Voge, S. McDonnel, G. J. Hughes, M. Milojevic, B. Lee, F. S. Aguirre-Tostado, K. J. Choi, H. C. Kim, J. Kim, and R. M. Wallace, “GaAs interfacial self-cleaning by atomic layer deposition,” Appl. Phys. Lett., vol. 92, p. 071901, 2008.
[26] Hang Dong Lee, Tian Feng, Lei Yu, Daniel Mastrogiovanni, Alan Wan, Torgn Gustafsson, and Eric Garfunkel, “Reduction of native oxides on GaAs during atomic layer growth of Al2O3,” Appl. Phys. Lett., vol. 94, p.222108, 2009.
[27] M. Milojevic, C. L. Hinkle, F. S. Aguirre-Tostado, H. C. Kim, E. M. Vogel, J. Kim, and R. M. Wallace, “Half-cycle atomic layer deposition reaction studies of Al2O3 on (NH4)2S passivated GaAs(100) surfaces,” Appl. Phys. Lett., vol. 93, p.252905, 2008.
[28] D. S. L. Mui, D. Biswas, J. Reed, A. L. Demirel, S. Strite, and H. Morkoc, “Investigations of the Si3N4/Si/n-GaAs insulator-semiconductor interface with lowinterface trap density,” Appl. Phys. Lett., vol. 60, p. 2511, 1992.
[29] Z. Chen and D. Gong, “Physical and electrical properties of a Si3N4/Si/GaAs metal–insulator–semiconductor structure,” J. Appl. Phys., vol. 90, p. 4205, 2001.
[30] M. Xu, K. Xu, R. Contreras,) M. Milojevic, T. Shen, O. Koybasi, Y.Q. Wu, R.M.Wallace, and P. D. Ye, “New Insight into Fermi-Level Unpinning on GaAs: Impact of Different Surface Orientations,” Tech. Dig. Int. Electron Devices Meet., p. 865, 2009.
[31] A. Jaouad, V. Aimez, C. Aktik, K. Bellatreche, and A. Souifi, “Fabrication of (NH4)2S passivated GaAs metal-insulator-semiconductor devices using low-frequency plasma-enhanced chemical vapor deposition,” J. Vac. Sci. Technol. A, vol. 22, p. 1027, 2004.
[32] M.-K. Lee, C.-F. Yen, J.-J. Huang, and S.-H. Lin, “Electrical characteristics of postmetallization-annealed MOCVD-TiO2 films on ammonium sulfide-treated GaAs,” J. Electrochem. Soc., vol. 153, p. F266, 2006.
[33] M. Passlack, J. K. Abrokwah, Z. Yu, R. Droopad, C. Overgaard, H. Kawayoshi, “Thermally induced oxide crystallinity and interface destruction in Ga2O3–GaAs structures,” Appl. Phys. Lett., vol. 82, p. 1691, 2003.
[34] C. L. Hinkle, A. M. Sonnet, E. M. Vogel, S. McDonnell, G. J. Hughes, M. Milojevic, B. Lee, F. S. Aguirre-Tostado, K. J. Choi, H. C. Kim, J. Kim, and R. M. Wallace,” GaAs interfacial self-cleaning by atomic layer deposition,” Appl. Phys. Lett., vol. 92, p. 071901, 2008.
[35] H. Hasegawa and H. Ohno, ” Unified disorder induced gap state model for insulator- semiconductor and metal–semiconductor interfaces,” J. Vac. Sci. Technol. B, vol. 4, p. 1130, 1986.
[36] R. Chau, Challenges and opportunities of III–V nanoelectronics for future logic applications (invited plenary talk), in: Conference Digest of IEEE Device Research Conference, University Park, PA, USA, p. 3 June 26–28, 2006 .
[37] R. Chau, S. Datta, M. Doczy, B. Jin, J. Kavaliers, A. Majumdar, M. Metz, M. Radosavljevic, IEEE Trans. Nanotechnol., vol. 4, p. 153, 2005.
[38] See Int. Technol. Roadmap for Semiconductors 2007 Edition for “Process Integration, Devices and Structures” at http://www.itrs.net/Links/2007ITRS/Home2007.htm.
[39] D. Kuzum, A. J. Pethe, T. Krishnamohan, and K. C. Saraswat, “Ge (100) and (111) n- and p-FETs with high mobility and low-T mobility characterization,” IEEE Trans. Electron Devices, vol. 56, p. 648, 2009.
[40] P. Zimmerman, G. Nicholas, B. De Jaeger, B. Kaczer, A. Stesmans, L.-A. Ragnarsson, D. P. Brunco, F. E. Leys, M. Caymax, G. Winderickx, K. Opsomer, M. Meuris, and M. M. Heyns, “High performance Ge p-MOS devices using a Si-compatible process flow,” Tech. Dig. Int. Electron Device Meet., p. 655, 2006.
[41] H.-C. Chin, M. Zhu, Z.-C. Lee, X. Liu, K.-M. Tan, H. K. Lee, L. Shi, L.-J. Tang, C.-H. Tung, G.-Q. Lo, L.-S. Tan, and Y.-C. Yeo, “A new silane-ammonia surface passivation technology for realizing inversion-type surface-channel GaAs n-MOSFET with 160 nm gate length and high-quality metal-gate/high-k dielectric stack,” Tech. Dig. Int. Electron Devices Meet., p. 383, 2008.
[42] M. Xu, K. Xu, R. Contreras, M. Milojevic, T. Shen, O. Koybasi, Y.Q. Wu, R.M. Wallace, and P. D. Ye, “New Insight into Fermi-Level Unpinning on GaAs: Impact of Different Surface Orientations,” Tech. Dig. Int. Electron Devices Meet., p. 865, 2009.
[43] N. Goel, D. Heh, S. Koveshnikov, I. Ok, S. Oktyabrsky, V. Tokranov, R. Kambhampati, M. Yakimov, Y. Sun, P. Pianetta, C.K. Gaspe, M.B. Santos, J. Lee, S. Datta, P. Majhi, and W. Tsai, “Addressing the gate stack challenge for high mobility InxGa1-xAs channels for FETs,” Tech. Dig. Int. Electron Devices Meet., p. 363, 2008.
[44] M. Radosavljevic, T. Ashley, A. Andreev, S. D. Coomber, G. Dewey, M. T. Emeny, M. Fearn, D. G. Hayes, K. P. Hilton, M. K. Hudait, R. Jefferies, T. Martin, R. Pillarisetty, W.
Rachmady, T. Rakshit, S. J. Smith, M. J. Uren, D. J. Wallis, P. J. Wilding and R. Chau, “High-performance 40nm gate length InSb p-channel compressively strained quantum well field effect transistors for low-power (Vcc=0.5V) logic applications,” Tech. Dig. Int. Electron Devices Meet., p. 727, 2008.
[45] P. D. Ye, “Main determinants for III–V metal-oxide-semiconductor field-effect transistors (invited),” J. Vac. Sci. Technol. A., vol. 26, p. 697, 2008.
[46] F. Zhu, H. Zhao, I. Ok, H. S. Kim, J. Yum, J. C. Lee, N. Goel, W. Tsai, C. K. Gaspe, and M. B. Santos, “Effects of anneal and silicon interface passivation layer thickness on device characteristics of In0.53Ga0.47As metal-oxide-semiconductor field-effect transistors,” Electrochem. Solid-State Lett., vol. 12, p. H131, 2009.
[47] H.-C. Chin, M. Zhu, X. Liu, H.-K. Lee, L. Shi, L.-S. Tan, and Y.-C. Yeo, “Silane- ammonia surface passivation for gallium arsenide surface-channel n-MOSFET,” IEEE Electron Device Lett., vol. 30, p. 110, 2009.
[48] C.-C. Cheng, C.-H. Chien, G.-L. Luo, C.-H. Yang, C.-K. Tseng, H.-C. Chiang, and C.-Y. Chang, “Improved electrical properties of Gd2O3/GaAs capacitor with modified wet-chemical clean and sulfidization procedures,” J. Electrochem. Soc., vol. 155, p. G56, 2008.
[49] C. L. Hinkle, A. M. Sonnet, E. M. Vogel, S. McDonnell, G. J. Hughes, M. Milojevic, B. Lee, F. S. Aguirre-Tostado, K. J. Choi, H. C. Kim, J. Kim, and R. M. Wallace, “GaAs interfacial self-cleaning by atomic layer deposition,” Appl. Phys. Lett., vol. 92, p. 071901, 2008.
[50] Hang Dong Lee, Tian Feng, Lei Yu, Daniel Mastrogiovanni, Alan Wan, Torgny Gustafsson, and Eric Garfunkel, “Reduction of native oxides on GaAs during atomic layer growth of Al2O3,” Appl. Phys. Lett., vol. 94, p. 222108, 2009.
[51] M. Milojevic, C. L. Hinkle, F. S. Aguirre-Tostado, H. C. Kim, E. M. Vogel, J. Kim, and R. M. Wallace, “Half-cycle atomic layer deposition reaction studies of Al2O3 on
(NH4)2S passivated GaAs(100) surfaces ,” Appl. Phys. Lett., vol. 93, p. 252905, 2008.
[52] Fischetti M. V., Wang L., Yu B., Sachs, Asbeck P. M., Taur Y., and Rodwell M., "Simulation of electron transport in high-mobility MOSFETs: density of states Bottleneck and source starvation,” Int. Electron Devices Meet. Tech. Dig., 2007, pp.109–112.
[53] Levinshtein M., Rumyantsev S., and Shur M., ”Handbook Series on Semiconductor Parameters Volume 1: Si, Ge, C(diamond), GaAs, GaP, GaSb, InAs, InP, InSb,” World
Scientific, Singapore, p. 77–82, 1996.