在本論文中，我們先利用多晶矽-氧化矽-氮化矽-氧化矽-單晶矽型式(SONOS-type)的電容平帶電壓變化，探討氧化鋁(Al2O3)與二氧化鉿(HfO2)在二氧化矽(SiO2)的接面上產生的”本質電偶極”(intrinsic dipole)。我們發現當氧化鋁或二氧化鉿沉積在二氧化矽上會使電容的平帶電壓變大，反之若是二氧化矽沉積在氧化鋁或二氧化鉿會使其平帶電壓變小。我們也發現氧化鋁產生的本質電偶極大約是二氧化鉿的兩倍。接下來將這個結果運用在二氧化鉿的奈米結晶粒的非揮發性快閃記憶體元件，發現元件的電容平帶帶壓變化有相同的結果，但由於此次實驗元件有很嚴重的閘極注入電子，使元件在福勒-諾德漢穿隧(Fowler Nordheim tunneling)抹除操作時無法正常運作，但接下來的實驗中我們將解決此問題。
再者，我們利用了高介電係數材料(Al2O3,HfAlOx)取代二氧化矽當作阻絕氧化層運用在奈米微晶粒(nanocrystal)的非揮發性的快閃記憶體元件，經過測試我們發現這層高介電常數材料並不會因會我們的離子佈值後退火產生嚴重的劣化。我們驗證介電係數越高的阻絕氧化層材料記憶體操作速度亦越快，但由於此高介電係數材料中的缺陷，使我們在抹除操作時有暫態的現象。此元件擁有很快的寫入速度(programmin speed)，同時也有很高的資料保持度(retention)，在經過一萬次的寫入抹除操作下(endurance)依然可以維持很好的記憶體效果。
最後，我們結合了之前的分析，將本質電偶極(Al2O3, HfO2)沉積在穿隧氧化層上，且運用高介電係數材料(Al2O3)的阻絕氧化層，做出多晶矽-氧化鋁-氮化矽-氧化矽-單晶矽型式的非揮發性記憶體元件。我們發現元件的臨界電壓會因電偶層存在而變大。我們分別利用福勒-諾德漢穿隧(Fowler Nordheim tunneling)與熱載子注入(hot carrier injection)兩種操作方式探討此電偶層對於元件的寫入與抹除的情況，並且探討其資料保(retention)度與元件的容忍度(endurance)和擾亂程度(disturbance)的影響。

In this thesis, we first study the influence of the presence of “intrinsic dipole” on the electrical properties of a SONOS-type nonvolatile memory (NVM) by a capacitor structure. The magnitudes of “intrinsic dipole” were extracted by the VFB shift observed in the C-V curves of the capacitors with adding Al2O3 or HfO2 inside the standard gate stack structure of a SONOS-type NVM, i.e., SiO2/Si3N4/SiO2. We found that VFB shifted toward positive direction when Al2O3 or HfO2 were deposited on top of SiO2 (tunneling layer). In contrast, VFB shifted toward negative direction when Al2O3 or HfO2 was deposited on top of Si3N4 (blocking layer). In addition, the magnitude of VFB shift for Al2O3 was about twice larger than HfO2. Next we also applied this scheme to the HfO2 nanocrystal SONOS-type NVM, and found that the tendency of VFB shift in the HfO2 nanocrystal NVM was the same with the conventional SONOS NVM. However, there was a serious gate injection problem in our device, so the fabricated devices can not be normally erased by FN-tunneling. We would tackle this problem in later chapters.
Then, we adopted the high-k material (Al2O3, HfAlOx) to replace the traditional SiO2 as blocking layer for the HfO2 nanocrystal NVM. With high thermal budget processing for device fabrication, the high-k materials sustained pretty well and did not depict visible degradation. We exhibited the HfAlOx as blocking layer having faster programming and erasing speed. However, there were plentiful defects in the HfAlOx layer, and this made our device have “transient phenomenon” during erase operation. For our nanocrystal memory devices, there were advantages of fast programming speed, excellent data retention time at room temperature, and superior endurance after P/E cycles of 104.
Finally, we adopted the intrinsic dipole scheme, i.e., depositing additional Al2O3 and HfO2 on top of tunneling oxide and used Al2O3 as blocking layer to make the so called SANOS-type NVM. The presence of dipole reflected on the observed larger device threshold voltage than the conventional one. Here we use both the FN-tunneling and hot carrier injection to study the electrical characteristics of the fabricated devices. We found that FN-tunneling operation has led to better endurance than hot carrier injection operation. Moreover, we also discussed the impact of dipole engineering on the retention and disturbance characteristics of our newly-developed nonvolatile memories.

Chapter 1 Introduction 1
1.1 Overview of Nonvolatile Memory 1
1.2 Motivation 5
1.3 Organization of the Thesis 6
Reference 7

Chapter 2 Effect of Interfacial Dipole on SONOS-type Memory Capacitors and Nanocrystals Memory Devices 15
2.1 Introduction 15
2.2 Experiment 16
2.3 Results and Discussion 17
2.3.1 Effect of Interfacial Dipole on SONOS-type Capacitor
17
2.3.2 Effect of Interfacial Dipole on Nanocrystal Memory Device 19
2.4 Summary 19
Reference 20


Chapter 3 Characteristic of HfO2 Nanocrystals Nonvolatile Flash Memory with High-k Blocking Layer 39
3.1 Introduction 39
3.2 Experiment 40
3.3 Results and Discussion 40
3.3.1 Material Analysis of Al2O3 and HfAlOx Blocking Layer
40
3.3.2 Characteristics of Program/Erase Operation 42
3.3.3 Transient Phenomenon of Erasing Operation 42
3.3.4 Data Retention 43
3.3.5 Endurance 44
3.4 Summary 44
Reference 45

Chapter 4 SANOS Nonvolatile Memory Devices with Dipole Layer Engineering 64
4.1 Introduction 64
4.2Experiment 64
4.3 Results and Discussion 65
4.3.1 Characteristics of Program/Erase Operation 65
4.3.2 Retention 67
4.3.3 Endurance 68
4.3.4 Disturbance 68
4.4 Summary 69
Reference 70

Chapter 5 Conclusions and Further Recommendations ....………………………………86
5.1 Conclusions ………………………………………………….……………….……..86
5.2 Further Recommendations ………………………………………………….………87

Vtia ……………………………………………………………………………….….………88

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