|
1. Jaume, S. and F.H. Charles, CMOS Electronics: How It Works, How It Fails. 2004: John Wiley \& Sons. 2. Huang, S.Y., Diagnosis of Byzantine Open-Segment Faults, in Test Symposium, 2002. Proceedings. 11th Asian. 2002. p. 248-253. 3. Wei, Z., C. Wu-Tung, and S.M. Reddy. Interconnect Open Defect Diagnosis with Physical Information. in Test Symposium, 2006. ATS '06. 15th Asian. 2006. 4. Laung-Terng, W., C.-W. WU, and X. WEN, eds. VLSI Test Principles and Architectures: Design for Testability. 2006, Elsevier Morgan Kaufmann Publishers: Boston. 5. Tafertshofer, P. and A. Ganz. SAT based ATPG using fast justification and propagation in the implication graph. in Computer-Aided Design, 1999. Digest of Technical Papers. 1999 IEEE/ACM International Conference on. 1999. 6. Roth, J., Diagnosis of automata failures: A calculus and a methods. 1966, IBM. p. 278-291. 7. Goel, P., an implicit enumeration algorithm to generate tests for combinational logic circuits. IEEE Trans. Comput, 1981: p. 215-222. 8. Larrabee, T., Test pattern generation using Boolean satisfiability. Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, 1992. 11(1): p. 4-15. 9. Chess, B. and T. Larrabee, Creating small fault dictionaries [logic circuit fault diagnosis]. Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, 1999. 18(3): p. 346-356. 10. Jue, W. and E.M. Rudnick, Bridge fault diagnosis using stuck-at fault simulation. Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, 2000. 19(4): p. 489-495. 11. Abramovici, M., P.R. Menon, and D.T. Miller, Critical Path Tracing: An Alternative to Fault Simulation. Design & Test of Computers, IEEE, 1984. 1(1): p. 83-93. 12. Waicukauski, J.A. and E. Lindbloom, Failure diagnosis of structured VLSI. Design & Test of Computers, IEEE, 1989. 6(4): p. 49-60. 13. Kuehlmann, A., et al. Error Diagnosis for Transistor-Level Verification. in Design Automation, 1994. 31st Conference on. 1994. 14. Shi-Yu, H., et al. ErrorTracer: a fault simulation-based approach to design error diagnosis. in Test Conference, 1997. Proceedings., International. 1997. 15. Shi-Yu, H. On improving the accuracy of multiple defect diagnosis. in VLSI Test Symposium, 19th IEEE Proceedings on. VTS 2001. 2001. 16. Fujiwara, H. and T. Shimono, On the Acceleration of Test Generation Algorithms. Computers, IEEE Transactions on, 1983. C-32(12): p. 1137-1144. 17. Pomeranz, I. and S.M. Reddy. On the generation of small dictionaries for fault location. in Computer-Aided Design, 1992. ICCAD-92. Digest of Technical Papers., 1992 IEEE/ACM International Conference on. 1992. 18. Camurati, P., et al. A diagnostic test pattern generation algorithm. in Test Conference, 1990. Proceedings., International. 1990. 19. Hartanto, I., et al. Diagnostic test pattern generation for sequential circuits. in VLSI Test Symposium, 1997., 15th IEEE. 1997. 20. Xue, H., C. Di, and J.A.G. Jess. Probability analysis for CMOS floating gate faults. in European Design and Test Conference, 1994. EDAC, The European Conference on Design Automation. ETC European Test Conference. EUROASIC, The European Event in ASIC Design, Proceedings. 1994. 21. Rodriguez-Montanes, R., et al. Diagnosis of Full Open Defects in Interconnecting Lines. in VLSI Test Symposium, 2007. 25th IEEE. 2007. 22. Needham, W., C. Prunty, and Y. Eng Hong. High volume microprocessor test escapes, an analysis of defects our tests are missing. in Test Conference, 1998. Proceedings., International. 1998. 23. Henderson, C.L., J.M. Soden, and C.F. Hawkins. THE BEHAVIOR AND TESTING IMPLICATIONS OF CMOS IC LOGIC GATE OPEN CIRCUITS. in Test Conference, 1991, Proceedings., International. 1991. 24. Makki, R.Z., S. Shyang-Tai, and T. Nagle. Transient power supply current testing of digital CMOS circuits. in Test Conference, 1995. Proceedings., International. 1995. 25. Konuk, H., Voltage- and current-based fault simulation for interconnect open defects. Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, 1999. 18(12): p. 1768-1779. 26. Spinner, S., et al. Automatic Test Pattern Generation for Interconnect Open Defects. in VLSI Test Symposium, 2008. VTS 2008. 26th IEEE. 2008. 27. Xijiang, L. and J. Rajski. Test Generation for Interconnect Opens. in Test Conference, 2008. ITC 2008. IEEE International. 2008. 28. Hillebrecht, S., et al. Extraction, Simulation and Test Generation for Interconnect Open Defects Based on Enhanced Aggressor-Victim Model. in Test Conference, 2008. ITC 2008. IEEE International. 2008. 29. Devtaprasanna, N., et al. Test Generation for Open Defects in CMOS Circuits. in Defect and Fault Tolerance in VLSI Systems, 2006. DFT '06. 21st IEEE International Symposium on. 2006. 30. Gomez, R., A. Giron, and V.H. Champac, A Test Generation Methodology for Interconnection Opens Considering Signals at the Coupled Lines. J Electron Test, 2008: p. 529-538. 31. Shi-Yu, H. Diagnosis of Byzantine open-segment faults [scan testing]. in Test Symposium, 2002. (ATS '02). Proceedings of the 11th Asian. 2002. 32. Chen-Yuan, K., L. Chien-Hui, and C.H.P. Wen. An ILP-Based Diagnosis Framework for Multiple Open-Segment Defects. in Microprocessor Test and Verification (MTV), 2009 10th International Workshop on. 2009. 33. Renovell, M. and G.N. Cambon, Electrical analysis and modeling of floating-gate fault. Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, 1992. 11(11): p. 1450-1458. 34. Lu, X. and W. Shi. Layout and Parasitic Information for ISCAS Circuits. 2004 [cited; Available from: http://dropzone.tamu.edu/~xiang/iscas.html.
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