(3.229.120.26) 您好!臺灣時間:2021/04/10 22:00
字體大小: 字級放大   字級縮小   預設字形  
回查詢結果

詳目顯示:::

我願授權國圖
: 
twitterline
研究生:鍾孝澤
研究生(外文):Hsiao-Tse Chung
論文名稱:一個高效能固態硬碟控制器的設計與硬體實作
論文名稱(外文):A High Performance Solid-State Disk Controller Design and Hardware Implementation
指導教授:陳慶瀚陳慶瀚引用關係
指導教授(外文):Ching-Han Chen
學位類別:碩士
校院名稱:國立中央大學
系所名稱:資訊工程研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2011
畢業學年度:99
語文別:中文
論文頁數:73
中文關鍵詞:快閃記憶體固態硬碟嵌入式系統
外文關鍵詞:FlashEmbeddedFTLDiskSSD
相關次數:
  • 被引用被引用:0
  • 點閱點閱:272
  • 評分評分:系統版面圖檔系統版面圖檔系統版面圖檔系統版面圖檔系統版面圖檔
  • 下載下載:0
  • 收藏至我的研究室書目清單書目收藏:0
典型的固態硬碟控制器多採用處理器作為快閃記憶體管理之核心,以執行FTL中介軟體(middleware)。FTL演算法主要目標在於有效管理快閃記憶體,這些演算法通常具有很高的計算複雜度,使得處理器難以負荷,或者使用更高速的處理器導致耗電和成本攀升。本論文所提出的固態硬碟控制器,是將FTL演算法設計成高效能的硬體核心,以實現一個不需要使用處理器的高速硬體化固態硬碟控制器,以硬體加速的方式縮短運行演算法時所耗費的時間,藉此來提高整體控制器的性能,同時可以降低功耗。
我們以階層式和模組化的系統化設計方法來進行此一複雜演算法的硬體設計,同時採用GRAFCET建模來描述每一模組的離散事件行為,最後將其合成為VHDL-based硬體IP,並於FPGA平台進行實體驗證,以此硬體化固態硬碟控制器整合到現有的固態硬碟系統架構中,實驗證明,相對於使用8位元處理器的FTL控制器,我們的系統可縮短整體存取時間33%,同時可以降低29%的功耗。
A typical Solid-State Disk controller usually uses a processor as the core of flash memory management that can execute Flash Translation Layer middleware. The purpose of FTL algorithm is to manage flash memory effectively. Generally, these algorithms which have high computational complexity cause the processor difficult to load. Some use the high performance processor to put up with the complexity of algorithms, which will lead to increasing power consumption and cost. The Solid-State Disk controller that this paper proposes is design FTL algorithm to be a core of high performance hardware to achieve a high speed hardware-based Solid-State Disk controller. With this method, it can decrease the time in running the algorithm to improve the performance of the controller while reducing power consumption.
We use hierarchical and modular system design method to design the hardware of the complex algorithm, and meanwhile we use GRAFCET modeling to describe the behavior of discrete event of each module. Finally we synthesize the design to VHDL-based hardware intelligent property and verify it on FPGA platform, integrating this hardware-based Solid-State Disk controller into the existing Solid-State system architecture. The experiments show that compared with the controller that uses 8-bit processor to run FTL algorithm, our system can reduce 33% of the access time and 29% of power consumption.
摘 要 I
ABSTRACT II
誌 謝 III
目 錄 IV
圖 目 錄 VI
表 目 錄 VIII
第一章、緒論 1
1.1 研究動機 4
1.2 論文結構 5
第二章、文獻探討 6
2.1 快閃記憶體管理相關文獻回顧 6
2.1.1 BAST演算法 7
2.1.2 FAST演算法 8
2.1.3 LAST演算法 9
2.1.4 SBAST演算法 10
2.2 固態硬碟效能評比相關文獻 11
第三章、固態硬碟控制器設計原理 13
3.1 快閃記憶體特性與控制原理 13
3.1.1 寫入控制 18
3.1.2 讀取控制 19
3.1.3 抹除控制 21
3.1.4 快閃硬碟控制器設計 22
3.2 固態硬碟控制器架構 22
第四章、FTL控制器設計 24
4.1 FTL演算法嵌入式軟體 25
4.1.1 MIAT51介紹 26
4.1.2 嵌入式軟體實作 26
4.2 FTL控制器硬體合成 31
第五章、系統實作與驗證 35
5.1 實驗平台 35
5.2 FTL嵌入式軟體控制器實驗 37
5.3 FTL硬體化控制器實驗 38
5.4 實驗結果與討論 41
第六章、結論 44
6.1 結論 44
6.2 未來展望 44
參考文獻 45
附錄一 47
GRAFCET of NAND_FLASH_ERASE Controller 47
GRAFCET of NAND_FLASH_PROGRAM Controller 48
GRAFCET of NAND_FLASH_READ Controller 49
附錄二 50
GRAFCET of Mapping Operations 50
GRAFCET of Read Operations 56
GRAFCET of Merge Operations 58
GRAFCET of Write Operations 62
[1]Samsung Semiconductor, http://www.samsung.com/global/business/semiconductor/productList.do?fmly_id=672
[2]Jen-Wei HSIEH, CSIE, NTUST, Introduction to Flash-Memory Storage Systems
[3]www.overoll.com, http://www.overoll.com/Content/WD-releases-its-first-consumer-SSD-/2010/3/4/194175.news?from=gimage
[4]N. Agrawal, V. Prabhakaran, T. Wobber, J. D. Davis, M. Manasse, R. Panigrahy, "Design tradeoffs for SSD performance", proceedings of the Usenix Annual Technical Conference, June 2008.
[5]A. Birrell, M. Isard, C. Thacker, T. Wobber, "A design for high-performance flash disks", SIGOPS Oper. Syst. Rev. 41(2), p.88-93 ,2007.
[6]J. U. Kang, J. S. Kim, C. Park, H. Park, J. Lee, "A multi-channel architecture for high-performance NAND flash-based storage system", Journal of Systems Architecture: the EUROMICRO Journal, vol.53 no.9, p.644-658, September, 2007.
[7]E. Gal , S. Toledo, "Algorithms and data structures for flash memories", ACM Computing Surveys (CSUR), vol.37 no.2, p.138-163, June 2005.
[8]A. Ban 1995. "Flash file system". United States Patent, No. 5,404,485, April.
[9]A. Ban 1999. "Flash file system optimized for page mode flash technologies", United States Patent, 5,937,425, August.
[10]J. Kim, J. M. Kim, S. H. Noh , S. L. Min, Y. Cho, "A space-efficient flash translation layer for compact-flash systems." ,IEEE Transactions on Consumer Electronics vol.48, no. 2, May 2002.
[11]S. W. Lee, D. J. Park, T. S. Chung, D. H. Lee, S. Park, H. J. Song, "A log buffer-based flash translation layer using fully-associative sector translation", ACM Transactions on Embedded Computing Systems (TECS), vol.6 no.3, July 2007.
[12]D. Narayanan, E. Thereska, A. Donnelly, S. Elnikety, A. Rowstron, "Migrating enterprise storage to SSDs: analysis of tradeoffs", Microsoft Research Ltd. Technical Report MSR-TR-2008-169, November 2008.
[13]S. W. Lee, B. Moon, C. Park, J. M. Kim, S. W. Kim. "A case for flash memory ssd in enterprise database applications", SIGMOD, p.1075-1086, 2008.
[14]Samsung Electronics CO., LTD, K9G8G08U0M Data sheets.
[15]Intel, http://www.intel.com/cd/corporate/pressroom/apac/zht/date/2008/400629.htm
[16]T. S. Chung, D. J. Park, S. W. Park, D. H. Lee, S. W. Lee, and H. J. Song 2006 System software for flash memory: A survey. In Proceedings of the 2006 IFIP International Conference on Embedded And Ubiquitous Computing (EUC 2006). (Aug.) Seoul, Korea.
[17]S. Lee, D. Shin, Y. Kim, and J. Kim, "Last: locality-aware sector translation for NAND flash memory-based storage systems", In Proc. Of IEEE International Workshop on Storage and I/O Virtualization, Performance, Energy, Evaluation and Dependability (SPEED08), 2008.
[18]I. Shin, “Light Weight Sector Mapping Scheme for NAND-based Block Devices”, IEEE Transactions on Consumer Electronics, Vol. 56, No. 2, May 2010
[19]Altera, DE2-115 User Manual
[20]Altera Quartus II v10.1, http://www.altera.com/products/software/quartus-ii/subscription-edition/qts-se-index.html
[21]ModelSim-Altera, http://www.altera.com/products/software/quartus-ii/modelsim/qts-modelsim-index.html
[22]Keil C51, http://www.keil.com/c51/
QRCODE
 
 
 
 
 
                                                                                                                                                                                                                                                                                                                                                                                                               
第一頁 上一頁 下一頁 最後一頁 top
系統版面圖檔 系統版面圖檔