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研究生:林世坤
研究生(外文):Shih-kun Lin
論文名稱:可配置2×2,4×4,與8×8資料串流之K最佳多輸入輸出解碼器
論文名稱(外文):Design of Configurable K-Best MIMO Detector for 2×2, 4×4, and 8×8 Data Streams
指導教授:薛木添
指導教授(外文):Muh-tian Shiue
學位類別:碩士
校院名稱:國立中央大學
系所名稱:電機工程研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2011
畢業學年度:99
語文別:中文
論文頁數:76
中文關鍵詞:多輸入輸出解碼可配置離散K最佳演算法連續干擾消除
外文關鍵詞:MIMO detectionconfigurabledistributed K-best algorithm (DKB)successive interference canstellation (SIC)
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在此論文裡,我們提出了可適用於8×8、4×4 和 2×2不同的天線組態,以及可支援64-QAM、16-QAM和QPSK不同的調變方法且K值可支援10和5的K最佳多輸入輸出解碼器。我們的設計運用了離散K最佳演算法(Distributed K-best, DKB)來減少傳統K最佳演算法每層的拜訪點從K√M到2K-1點,為了進一步減少拜訪的點數,又使用了連續干擾消除(Successive Inference Constellation, SIC)取代某些特定層數的DKB。在硬體的實現上,我們利用DKB與SIC的組合方塊來達到管線式架構可配置的需求。為了減少乘法器的複雜度,我們使用移位乘法器(Shift Multiplier, SM)來取代傳統的乘法器。本論文使用SMIMS VeriEnterprise Xilinx FPGA驗證電路功能,最後利用90-nm CMOS製程來實現所提出的可配置的多輸入輸出解碼器。該晶片核心面積為0.877×0.877mm2,當晶片操作在78.12 MHz以及1V的供應電壓和8×8 64QAM K=10的模式時其功率消耗僅16.5mW。
In this thesis, we proposed a MIMO detector which can support multiple antenna types (8×8, 4×4, and 2×2), various modulation schemes (64-QAM, 16-QAM, and QPSK) and two K-values (K=10 or K=5) for IEEE 802.16m standard. From the algorithm aspects, the adopted distributed K-best (DKB) algorithm can reduce the number of visited nodes at each layer from K√M to 2K-1, compared with the conventional K-best algorithm. To further reduce number of visited nodes, our design employs successive inference cancellation (SIC) in some specific layers to replace the DKB layer. In terms of hardware implementation, the DKB and SIC are designed as elementary building blocks. With these building blocks, the proposed MIMO detector can flexibly achieve the configurable architecture. In order to simplify the multiplier complexity, we propose a novel shift-multiplier (SM) to replace the conventional multiplier. The proposed configurable MIMO detector is verified by the SIMIS VeriEnterprise Xilinx FPGA development board. Finally, this design is fabricated in a 90-nm CMOS technology. The core area is 0.877 0.877 mm2. With the 1V supply voltage, the chip power is 16.5 mW in 8×8 64-QAM mode and its clock rate is 78.12 MHz.
摘要 i
Abstract ii
致謝 iii
目錄 iv
圖目錄 vi
表目錄 ix
第一章 緒論 1
1.1 背景 1
1.2 研究動機 2
1.3 論文架構 3
第二章 多輸入輸出系統 4
2.1 系統架構 4
2.2 多輸入輸出技術 6
2.2.1 發射分集 6
2.2.2 接收分集 8
2.2.3 波束成型 9
2.2.4 空間多工 10
2.3 空間多工解碼 11
2.3.1 線性解碼 11
2.3.2 非線性解碼 12
2.4 IEEE 802.16m規格簡介 15
第三章 K-最佳演算法 17
3.1 實數訊號模型 17
3.2 傳統K-最佳演算法 19
3.3 離散K-最佳演算法 20
3.3.1 演算法說明 20
3.3.2 星座點列舉法 22
3.3.3 天線組態可配置之系統架構 26
3.4 複雜度與效能比較分析 29
第四章 K-最佳演算法解碼器硬體電路設計 33
4.1 DKB硬體架構 33
4.2 FCU電路設計 35
4.2.1 移位乘法器 36
4.3 NCU電路設計 38
4.3.1 次子點列舉電路設計 39
4.4 連續干擾消除電路設計 41
4.5 天線可配置電路設計 41
第五章 晶片實現 43
5.1 設計流程 43
5.2 定點數分析 44
5.3 FPGA驗證 51
5.4 晶片設計結果 53
5.4.1 模擬結果驗證 53
5.4.2 晶片結論 55
5.5 硬體比較 58
第六章 結論 60
參考文獻 61
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