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研究生:許茹棋
研究生(外文):Ju-chi Hsu
論文名稱:利用先進標準元件庫資訊估測動態同步切換雜訊
論文名稱(外文):On Dynamic Simultaneous Switching Noise Analysis with Advanced Standard Library Information
指導教授:劉建男劉建男引用關係
指導教授(外文):Chien-nan Liu
學位類別:碩士
校院名稱:國立中央大學
系所名稱:電機工程研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2011
畢業學年度:99
語文別:中文
論文頁數:54
中文關鍵詞:電源電流波形估測標準元件庫同步切換雜訊電源供應雜訊
外文關鍵詞:power supply noisesimultaneous switching noisestandard librarysupply current waveform estimation
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  隨著積體電路製程技術進入到奈米(nanometer)的時代,電源完整性(power integrity)變成一項重要的議題。同步切換雜訊(simultaneous switching noise)是電源供應雜訊(power supply noise)的一個重要部份,隨著電路時脈速度和總電流密度的增加,同步切換雜訊會造成更嚴重的電源電壓變動。傳統上,要等到電晶體層級(transistor level)的模擬才能得知同步切換雜訊的大小,但對於複雜電路而言,其模擬的時間非常久,所以本篇論文提出了一個在閘級層(gate level)估測動態同步切換雜訊的方法。考慮電源雜訊的影響,由先進標準元件庫(standard cell library)得到的理想電源電流波形(supply current waveform),經由RLC低通濾波器轉換可得到修正的電流,利用此修正電流,就可藉由基本的電感公式求出同步切換雜訊。由於所需的資料皆可在閘級層得到,所以可以快速地得到估測結果。實驗結果顯示,我們所提出的電流修正方法可以明顯地改善電源雜訊估測的精準度,因此可幫助使用者在電路設計初期做初步的雜訊估測。
  As the integrated circuit process technology goes into the nanometer era, power integrity becomes an important issue. Simultaneous switching noise is a major component of the power supply noise. Due to the increased clock rate and current density, this noise would result in more serious voltage fluctuations in power network. Traditionally, the simultaneous switching noise can be analyzed by the transistor-level simulation only, which takes too much simulation time for complex circuits. Thus, this thesis proposes a method of estimating the dynamic simultaneous switching noise at gate level. In order to consider the power supply noise effects, the ideal supply current waveform obtained from the standard cell library is modified by a RLC low-pass filter transformation. With the modified current waveform, the simultaneous switching noise can be derived easily by using the basic formula of inductor. Because all the required input data of this method can be obtained at gate level, the estimation is very quick. The experimental results show that the accuracy of the estimation results can be significantly improved by the proposed approach. It can help users to do the preliminary noise estimation at early design stage.
摘 要 i
Abstract ii
致 謝 iii
目 錄 iv
圖目錄 v
表目錄 vii
一、緒論 1
1-1 電源供應雜訊 1
1-2 研究動機 5
1-3 論文組織 7
二、背景知識 8
2-1 估測同步切換雜訊的相關研究 8
2-2 標準元件庫的資訊 12
2-3 閘級層的電流波形估測方法 16
三、同步切換雜訊之估測方法 19
3-1 簡介 19
3-2 問題定義 19
3-3 同步切換雜訊估測流程 21
3-4 估測受電源雜訊影響的電流波形 24
3-4-1 利用先進標準元件庫估測理想電源電流波形 24
3-4-2 考慮電壓降的電流修正 26
3-4-3 考慮同步切換雜訊的電流修正 29
3-5 估測同步切換雜訊 32
四、實驗結果 33
4-1 實驗設定 33
4-2 比較對象 35
4-3 實驗數據 36
4-4 同步切換雜訊波形觀察 42
五、結論 43
參考文獻 44
[1] “Simultaneous Switching Noise and Signal Integrity,” Actel Corporation, 2006.
[2] M. Nourani, M. Tehranipoor, and N. Ahmed, “Pattern Generation and Estimation for Power Supply Noise Analysis,” in Proc. IEEE VLSI Test Symp., pp. 439–444, May 2005.
[3] W. H. Lee, S. Pant, and D. Blaauw, “Analysis and Reduction of On-Chip Inductance Effects in Power Supply Grids,” in Proc. Intl. Symp. Quality Electron. Des., pp. 131–136, Mar. 2004.
[4] N. Srivastava, X. Qi, and K. Banerjee, “Impact of On-chip Inductance on Power Distribution Network Design for Nanometer Scale Integrated Circuits,” in Proc. Intl. Symp. Quality Electron. Des., pp. 346–351, Mar. 2005.
[5] A. Muramatsu, M. Hashimoto, and H. Onodera, “Effects of On-chip Inductance on Power Distribution Grid,” in Proc. Intl. Symp. Physical Des., pp. 63–69, Apr. 2005.
[6] P. Heydari and M. Pedram, “Ground Bounce in Digital VLSI Circuits,” IEEE Trans. Very Large Scale Integr. Syst., vol. 11, no. 2, pp. 180–193, Apr. 2003.
[7] S. Zhao, K. Roy, and C.-K. Koh, “Decoupling Capacitance Allocation and Its Application to Power-Supply Noise-Aware Floorplanning,” IEEE Trans. Comput.- Aided Des. Integr. Circuits Syst., vol. 21, no. 1, pp. 81–92, Jan. 2002.
[8] “CCS Power Technical White Paper Version 3.0,” Synopsys, 2006.
[9] Y.-M. Jiang and K.-T. Cheng, “Analysis of Performance Impact Caused by Power Supply Noise in Deep Submicron Devices,” in Proc. Des. Autom. Conf., pp. 760–765, Jun. 1999.
[10] S. Kose and E. G. Friedman, “Fast Algorithms for Power Grid Analysis Based on Effective Resistance,” IEEE Intl. Symp. Circuits and Systems, pp. 3661–3664, May 2010.
[11] N. H. A. Ghani and F. N. Najm, “Fast Vectorless Power Grid Verification Under an RLC Model,” IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 30, no. 5, pp. 691–703, May 2011.
[12] M. Hekmat, S. Mirabbasi, and M. Hashemi, “Ground Bounce Calculation due to Simultaneous Switching in Deep Sub-micron Integrated Circuits,” IEEE Intl. Symp. Circuits and Systems, pp. 5617–5620, May 2005.
[13] K. T. Tang and E. G. Friedman, “Simultaneous Switching Noise in On-Chip CMOS Power Distribution Networks,” IEEE Trans. Very Large Scale Integr. Syst., vol. 10, no. 4, pp. 487–493, Aug. 2002.
[14] “Si2 Effective Current Source Model (ECSM) Timing and Power Specification Version 2.1.1,” Cadence Design Systems and Si2, 2006.
[15] M.-S. Lee and C.-N. J. Liu, “Dynamic Supply Current Waveform Estimation with Standard Library Information,” IEICE Trans. Fund. Electr., vol. E93-A, no. 3, pp. 595–606, Mar. 2010.
[16] M.-S. Lee, K.-S. Lai, C.-L. Hsu, and C.-N. J. Liu, “Dynamic IR Drop Estimation at Gate Level with Standard Library Information,” IEEE Intl. Symp. Circuits and Systems, pp. 2606–2609, May 2010.
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