(3.234.221.162) 您好!臺灣時間:2021/04/14 16:48
字體大小: 字級放大   字級縮小   預設字形  
回查詢結果

詳目顯示:::

我願授權國圖
: 
twitterline
研究生:王彥文
研究生(外文):Yan-wun Wang
論文名稱:三維積體電路中同步降低熱點溫度與電源雜訊之研究
論文名稱(外文):Simultaneous Hotspot Temperature and Supply Noise Reduction using Thermal TSVs and Decoupling Capacitors
指導教授:陳泰蓁
指導教授(外文):Tai-chen Chen
學位類別:碩士
校院名稱:國立中央大學
系所名稱:電機工程研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2011
畢業學年度:99
語文別:中文
論文頁數:60
中文關鍵詞:電源雜訊熱點溫度三維積體電路
外文關鍵詞:hotspot temperaturesupply noisethermal TSVsdecoupling capacitors
相關次數:
  • 被引用被引用:0
  • 點閱點閱:86
  • 評分評分:系統版面圖檔系統版面圖檔系統版面圖檔系統版面圖檔系統版面圖檔
  • 下載下載:0
  • 收藏至我的研究室書目清單書目收藏:0
隨著製程的演進,現今超大型積體電路的設計流程變得愈來愈複雜。正因製程技術上的精進,使得晶片的尺寸得以做得更小,但也同時讓整體的花費變得更高。三維積體電路設計主要強調的精神,是將晶片由傳統的二維平面擺放,延伸到可做垂直方向的放置,如此一來,在單位面積上的晶片密度可以得到提升,便可以用較低的花費或較成熟的技術製造相同功能的設計。此外,還可以將不同製程的電路設計,利用晶片堆疊的方式加入到三維積體電路架構當中,即是所謂異質整合的應用。
在三維積體電路設計架構中,熱的問題以及電源雜訊的問題將會影響到整體電路運作的效能。本論文提出一個同時處理兩個問題的方法,即加入改善熱點溫度的散熱型矽晶穿孔,以及加入改善電源雜訊的去耦合電容。由於散熱型矽晶穿孔在常溫下即有等效於去耦合電容的能力,且此能力會隨溫度上升而更加增強,因此散熱型矽晶穿孔不僅有散熱的功能且可以利用其電容性質改善電源雜訊。我們將散熱型矽晶穿孔的兩種功能模型化至我們提出的解決方法中,並且在不改變整體平面規劃的面積之下,利用線性規劃的方式,依照需求有效地達成降溫以及改善電源雜訊的問題。若是在現有的條件之下,無法達成設定的目標溫度或是改善的電源雜訊值,則會回報距離目標溫度或是尚需改善電源雜訊的差值。
As the process technology progresses, the design flow of VLSI circuits becomes more and more complicated. Although the enhancing technique makes the chip size reduce, the fabrication cost arises simultaneously. The difference between two dimensional(2D)and three dimensional integrated circuits(3D ICs)is that 3D ICs emphasize the vertical connection between layer and layer, which can certainly arise the chip density, implying that we can obtain the same design with lower cost. Besides, the die-stacking technology of 3D IC provides designs with different technologies on a chip and supports the application of heterogeneous integration.
In 3D IC architecture, the thermal and power noise problems affect the performance of the whole chip. In this thesis, we present a method to solve these two problems by simultaneously adding thermal TSVs(TTSVs)for thermal issue and decoupling capacitors(decaps)for power noise issue. Since the unit-area capacitance of a TTSV at the room temperature is equivalent to that of a decap, and the unit-area capacitance of a TTSV is arisen with increasing temperature, TTSVs have the abilities of dissipating thermal and reducing power noise. We model these two abilities into the proposed method. Without enlarging the area of floorplanning, the proposed method can maximize the reduction of the temperature and IR-drop using linear programming under the given target temperature and voltage. If the target temperature or voltage could not be achieved, the differences between the real temperature (voltage) and target temperature (voltage) will be reported.
摘要 ................................ ......................... i
Abstract Abstract ................................ ..................... ii
致謝 ................................ ........................ iii
目錄 ................................ ......................... iv
第一章、 簡介 ................................ ................. 1
1-1 三維積體電路設計 ................................ ........ 1
1-2 電源雜訊議題 ................................ ............ 2
1-3 散熱議題 ................................ ................ 4
1-4 相關研究 ................................ ................ 7
1-4-1 考慮去耦合電容 ................................ .... 7
1-4-2 考慮散熱型矽晶穿孔 ................................ 9
1-4-3 考慮去耦合電容與散熱型矽晶穿孔 .................... 9
1-5 研究動機 ................................ ............... 11
1-6 問題定義 ................................ ............... 12
1-7 論文結構 ................................ ............... 14
第二章、 背景 ................................ ................ 15
2-1 電源雜訊分析 ................................ ........... 15
2-2 溫度分析 ................................ ............... 17
2-3 線性規劃 ................................ ............... 18
第三章、 背景 ................................ ................ 20
3-1 流程圖 ................................ ................. 20
3-2 建構常規範圍型線性劃 ................................ . 23
3-2-1 符號定義 ................................ ......... 23
3-2-2 限制條件 ................................ ......... 25
3-2-3 權重值設定 ................................ ....... 27
3-2-4 多層架構下之熱點議題 ............................. 28
3-3 建構縮減範圍型線性規劃 ................................ . 33
3-3-1 去耦合電容有效降低雜訊之範圍設定 ................. 33
3-3-2 散熱型矽晶穿孔有效降低溫度之範圍設定 ............. 34
3-3-3 多層架構下之熱點議題 ............................. 35
第四章、 實驗結果與分析 ................................ ...... 40
4-1 實驗環境與設定 ................................ ......... 40
4-2 實驗結果 ................................ ............... 40
第五章、 結論與未來展望 ................................ ...... 43
參考文獻 ................................ ..................... 44
[1]R. Weerasekera, D. Pamunuwa, L.-R. Zheng, and H. Tenhunen, “Two-Dimensional and Three-Dimensional Integration of Heterogeneous Electronic Systems Under Cost, Performance, and Technological Constraints,” in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 28, no. 8, pages 1237-1250, Aug. 2009.
[2]M. Koyanagi, T. Fukushima, and T. Tanaka, “Three-Dimensional Integration Technology and Integrated Systems,” in Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference, pages 409-415, 2009.
[3]N. Miyakawa, “A 3D Prototyping Chip Based on a Wafer-Level Stacking Technology,” in Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference, pages 416-420, 2009.
[4]J.-Q. Lu, “3D Hyperintegration and Packing Technologies for Micro-Nano Systems,” in Proceeding of the IEEE, vol. 97, no. 1, pages 18-30, 2009.
[5]J. Cong, Z. Yan, “Thermal Via Planning for 3D ICs,” in IEEE/ACM International Conference on Computer-Aided Design, pages 165-172, 2005.
[6]T.-Y. Chiang, K. Banerjee, and K. C. Saraswat. ”Compact Modeling and SPICE-Based Simulation for Electrothermal Analysis of Multilevel ULSI Interconnects,” in IEEE International Conference on Computer-Aided Design, pages 165-172, 2001.
[7]S. Lee, T. Lemczyk, and M. Yovanovich. “Analysis of Thermal Vias in High Density Interconnect Technology,” in Proceedings 8th IEEE Semi-Therm Symposium, pages 55-61, Feb. 1992.
[8]G. Katti, A. Mercha, M. Stucchi, Z. Tokei, D. Velenis, J. Van Olmen, C. Huyghebaert, A. Jourdain, M. Rakowski, I. Debusschere, P. Soussan, H. Oprins, W. Dehaene, K. De Meyer, Y. Travaly, E. Beyne, S. Biesemans, B. Swinnen, “Temperature dependent electrical characteristics of Through-Si-Via (TSV) interconnections”, in IEEE International Interconnect Technology Conference, pages 1-3, 2010.
[9]S. Zhao, K. Roy, C.-K. Koh, “Decoupling Capacitance Allocation and Its Application to Power-Supply Noise-Aware Floorplanning,” in Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 21, no. 1, pages 81-92, Jan. 2002.
[10]E. Wong, J. Minz, K. L. Sung, “Decoupling Capacitor Planning and Sizing For Noise and Leakage Reduction,” in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 26, no. 11, pages 2023-2034, Nov. 2007.
[11]J.-T. Yan, Y. C. Chang, Z.-W. Chen, “Thermal Via Planning for Temperature Reduction in 3D ICs,” in Proceedings of IEEE SOC Conference, pages 392-395, 2010.
[12]E. Wong, J. Minz, K. L. Sung, “Effective Thermal Via and Decoupling Capacitor Insertion for 3D System-On-Package”, in Proceedings of Electronic Components and Technology Conference, pages 1795-1801, 2006.
[13]J. Cong, J. Wei, Y. Zhang, “A Thermal-Driven Floorplanning Algorithm for 3D ICs,” in IEEE International Conference on Computer-Aided Design, pages 306-313, 2004.
[14]CFD-ACE+ Module Manual, Vol. I, Version 2002.
[15]G. Ajwani, C. Chu, W.-K. Mak, “ISPD: FOARS: FLUTE Based Obstacle-Avoiding Rectilinear Steiner Tree Construction,” in Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 30, no. 2, pages 194-204, Feb. 2011.
[16]S. W. Ho, S. W. Yoon, Q. Zhou. K. Pasad, V. Kripesh, J. H. Lau, “High RF Performance TSV Silicon Carrier for High Frequency Application,” in Electronic Components and Technology Conference, pages 1946-1952, 2008.
[17]J. Choi, M. Swaminathan, D. Nhon, R. Master, “Modeling of Power Supply Noise in Large Chips Using the Circuit-Based Finite-Difference Time-Domain Method,” in Transactions on Electromagnetic Compatibility, vol. 47, no. 3, pages 424-439, Aug. 2005.
[18]C. Torregiani, H. Oprins, B. Vandevelde, E. Beyne, I. De Wolf, “Compact Thermal Modeling of Hot Spots in Advanced 3D-Stacked ICs,” in Electronics Packaging Technology Conference, pages 131-136, 2009.
QRCODE
 
 
 
 
 
                                                                                                                                                                                                                                                                                                                                                                                                               
第一頁 上一頁 下一頁 最後一頁 top
系統版面圖檔 系統版面圖檔