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研究生:許庭碩
研究生(外文):Ting-Shuo Hsu
論文名稱:可選擇功率消耗之500 MS/s快閃式類比數位轉換器
論文名稱(外文):A 500 MS/s Flash-ADC with Selectable Power Consumption
指導教授:陳勛祥陳勛祥引用關係
指導教授(外文):Hsun-Hsiang Chen
學位類別:碩士
校院名稱:國立彰化師範大學
系所名稱:積體電路設計研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2011
畢業學年度:99
語文別:英文
論文頁數:51
中文關鍵詞:快閃式類比數位轉換器比較器解析度功率消耗
外文關鍵詞:Flash-ADCcomparatorresolutionpower consumption
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本篇論文提出一快閃式類比數位轉換器,可提供使用者選擇六種不同的功率消耗,藉由輸入六種不同偏壓而得之。本篇論文使用傳統式Flash-ADC作為設計架構,對於比較器的部分,輸入六種不同的偏壓,將會得到六種不同的解析度與功率消耗。取樣頻率在500 MHz,供應電壓為1.8 V,使用Hspice及TSMC 0.18 μm CMOS製程進行模擬,當比較器輸入偏壓為0.85 V、0.9 V及1.0 V時ENOB皆為5以上,功率消耗分別為29.4mW、24.2 mW與16.3 mW;輸入偏壓為1.1 V、1.15 V、1.2 V時ENOB皆為4以上,功率消耗分別為9.67 mW、7.05 mW及6.6 mW。此外也針對三組不同的取樣頻率進行模擬,分別為400 MHz、250 MHz及200 MHz,個別對應到輸入偏壓為0.9 V、1.0 V及1.1 V時ENOB皆為5以上。
In this thesis, a 500M sample/s Flash-ADC is presented which can select 6 different power consumption from 6 different input Vbias. In comparator, we have 6 different input Vbias to obtain 6 different resolution and power consumption. In this study, we use TSMC 0.18 μm CMOS technology and 1.8V power supply to simulate the Flash-ADC. When sample rate is 500 MHz and input Vbias are 0.85 V, 0.9 V, 1.0 V, 1.1 V, 1.15 V and 1.2 V, the corresponding ENOB are 5.36, 5.31, 4.81, 4.57, 4.02 and 4. and the power consumptions are 29.4 mW, 24.2 mW, 16.3 mW, 9.67 mW, 7.05 mW, and 6.60 mW respectively. The simulation results show that the sample rate and Vbias are 400 MHz with 0.9 V, 250 MHz with 1.0 V and 200 MHz with 1.1 V, the ENOB are 5.54, 5.55 and 5.78, and the power consumption are 22.3 mW, 14.0 mW and 8.1 mW.
CONTENTS
摘要 i
Abstract ii
誌謝 iii
CONTENTS iv
LIST OF FIGURE vi
LIST OF TABLES viii

Chapter 1 Introduction 1
1-1 Motivation 1
1-2 Organization of Thesis 2

Chapter 2 Analog-to-Digital Converter 4
2.1 Introduction 4
2.2 Important design parameters of A/D converters 5
2.2.1 Offset error 5
2.2.2 Gain error 6
2.2.3 Differential nonlinearity (DNL) 6
2.2.4 Integral nonlinearity (INL) 7
2.2.5 Monotonic and Missing code 8
2.2.6 Signal-to-noise and distortion ratio 9
2.2.7 Effective number of bits 9
2.3 High speed A/D converter 10
2.3.1 Flash A/D converter 11
2.3.2 Two-step A/D converter 12
2.3.3 Pipeline A/D converter 14
2.3.4 Time-interleaves A/D converter 15
2.3.5 Folding A/D converter 16

Chapter 3 Design of Flash ADC 18
3-2 Vbias control circuit 19
3-3 Flash comparators 21
3-4 Latch 23
3-5 Encoder 24
3-5-1 DVL+ (Dual value logic+) 25

Chapter 4 Simulation 31
4-1 Flash ADC pre-simulation results 31
4-2 Flash ADC post-simulation results 38
4-2-1 Layout 38

Chapter 5 Conclusion and future works 46
5-1 Conclusion 46
5-2 Future works 46
Reference 47

LIST OF FIGURE
Figure 1-1. A/D converter with different speed and resolution 1
Figure 2-1. The basic N-bit ADC 4
Figure 2-2. Transfer characteristics for a 3-bit ADC with offset error 5
Figure 2-3. Transfer curve for 3-bit ADC with gain error 6
Figure 2-4. Transfer curve of ADC with DNL 7
Figure 2-5. ADC with non-monotonic transfer code 8
Figure 2-6. ADC with missing code 9
Figure 2-7. Flash A/D converter architecture 11
Figure 2-8. Two-step A/D converter architecture 13
Figure 2-9. Pipelined A/D converter architecture 14
Figure 2-10. Time-Interleaved A/D converter architecture 16
Figure 2-11. Transfer function of full-flash and folding ADC 17
Figure 2-12. Folding A/D converter architecture 17
Figure 3-1. A Flash-ADC with selectable power consumption 18
Figure 3-2. Vbias control circuit. 19
Figure 3-3. Vbias simulation result. 20
Figure 3-4. P-type differential comparator. 21
Figure 3-6. A 3-bit ROM-based encoder. 24
Figure 3-7. Tradition CMOS logic. 25
Figure 3-8. DVL+. 26
Figure 3-9. Logic when input are A and B. 27
Figure 3-10. Traditional CMOS logic gate about figure 3-9.27
Figure 3-11. DVL+ logic gate about figure 3-9. 28
Figure 3-12. DVL+ logic gate when input are A and B 28
Figure 4-1. Pre-simulation result when Vbias = 0.85 V. 31
Figure 4-2. Pre-simulation result when Vbias = 0.9 V. 32
Figure 4-3. Pre-simulation result when Vbias = 1.0 V. 32
Figure 4-4. Pre-simulation result when Vbias = 1.1 V. 33
Figure 4-5. Pre-simulation result when Vbias = 1.15 V. 33
Figure 4-6. Pre-simulation result when Vbias = 1.2 V. 34
Figure 4-7. The layout of a 500 MS/s Flash-ADC with selectable power consumption. 38
Figure 4-8. The floor plan of a 500 MS/s Flash-ADC with selectable power consumption without I/O Pad. 39
Figure 4-9. Post-simulation result when Vbias = 0.85 V. 41
Figure 4-10. Post-simulation result when Vbias = 0.9 V. 41
Figure 4-11. Post-simulation result when Vbias = 1.0 v. 42
Figure 4-12. Post-simulation result when Vbias = 1.1 V. 42
Figure 4-13. Post-simulation result when Vbias = 1.15 V.43
Figure 4-14. Post-simulation result when Vbias = 1.2 V. 43

LIST OF TABLES
Table 2.1. Main characteristic of A/D converters 10
Table 3.1. Digital code and Vbias relationship. 20
Table 3.2. The comparator power consumption at different Vbias voltages. 22
Table 3.3. The transistor numbers of different logic function implemented by DVL+ and tradition CMOS logic 26
Table 3.4. The truth table of figure 3-12 29
Table 3.5. Performance compared tradition CMOS Flash ADC with DVL+ Flash ADC. 30
Table 4.1. The proposed flash ADC simulation results 35
Table 4.2. 4 different sample rate simulation result. 36
Table 4.3 4 Corners simulation results of ENOB and power consumption. 37
Table 4.4. Pre-simulation results and post-simulation results. 44
Table 4.5 Compares the performance of the proposed ADC when Vbias equals 0.9 V with the referred Flash ADC. 45




Reference
[1] 王仕裕(民93)。八位元折疊式與插值式類比數位轉換器之研究。國立彰化師範大學墊子工程學系碩士論文,彰化市。
[2] S. Veeramachanen, A. M. Kumar, V. Tummala and M. B. Srinivas, “Design of a Low Power, Variable-Resolution Flash ADC,” VLSI Design, 2009 22nd International Conference, pp.117-122, 2009.
[3] M. Masoumi, E. Markert, U. Heinkel, G. Gielen, “Ultra low power flash ADC for UWB transceiver applications,” Circuit Theory and Design, 2009. ECCTD 2009. European Conference, pp.41-44, 2009
[4] M. O. Shaker, S. Gosh and M. A. Bayoumi, “A 1-GS/s 6-bit flash ADC in 90 nm CMOS,” Circuits and Systems, 2009. MWSCAS '09. 52nd IEEE International Midwest Symposium, pp.144-147, 2009.
[5] Y.-S. Hwang, J.-F. Lin, C.-C. Huang, J.-J. Chen and W.-T. Lee, “An efficient power reduction technique for flash ADC,” SOC Conference, 2007 IEEE International, pp.43-46, 2007.
[6] W. T. Lee, P. H. Huang, Y. Z. Liao and Y. S. Hwang, “A New Low Power Flash ADC Using Multiple-Selection Method,” Electron Devices and Solid-State Circuits, 2007. EDSSC 2007. IEEE Conference, pp.341-344, 2007.
[7] Y. Z. Lin, Y. T. Liu, and S. J. Chang, “A 5-bit 3.2-GS/s Flash ADC With a Digital Offset Calibration Scheme,” Very Large Scale Integration (VLSI) Systems, IEEE Transactions , pp.509-513, 2010.
[8] 吳健福(民93)。一個六位元每秒十億次取樣頻率的類比/數位轉換器。國立成功大學電機所儀器系統組碩士班碩士論文,台南市。
[9] Yi-Ting Huang, “A 6-bit 220-MS/s Successive-Approximation Analog-to-Digital Converter” Department of Electrical Engineering National Cheng Kung University Tainan, Taiwan, R.O.C thesis for Master of Science, December, 2008.
[10] 唐正哲(民97)。管線式類比數位轉換器設計。國立暨南大學電機工程學系碩士論文,南投縣。
[11] Yi-Jiun Chen, ”A Novel Low Power Two-step Flash Analog-to-digital converter” Department of Electrical Engineering National Cheng Kung University Tainan, Taiwan, R.O.C. Thesis for Master of science, July, 2008.
[12] Ming-Long Chuang, “A Flash ADC based single signal controlled VCO for the tuning of full band frequencies” A Thesis Submitted to the Graduate Institute of Integrated Circuit Design National Changhua University OF education in Partial Fulfillment of the Requirements for the Degree of Master of science, January, 2011.
[13] Roubik Gregorian, Introduction to CMOS OP-AMPs and comparators. Wiley, New York, 1999.
[14] He-Gong Wei, U-Fat chio, Sai-Weng Sin, Seng-Pan U, Martins R.P,.”A power scalable 6-bit 1.2GS/s flash ADC with power on/off Track-and-Hold and preamplifier,” Preceedings of IEEE International Symposium on Circuits and Systems, pp. 5-8, 2008.
[15] Shin-Chang Hsia, Wen-Ching Lee, “A New 6-bit Flash A/D Converter using Novel Two-Step Structure.” Proceedings of IEEE Design and Diagnostics of Electronic Circuits and Systems, pp. 101-105, 2006.
[16] Li Lin, Junyan Ren, Fan Ye, “A 600-msample/s, 25-mw, 6bit folding and
interpolating ADC in 0.13μm CMOS,” Proceedings of IEEE ASICON, pp.199-202, 2009.
[17] Fen-Chiu Hsieh, Tai-Cheng Lee, “A 6-bit pipelined analog-to-digital converter with current-switching open-loop residue amplification.” Proceedings of IEEE Asian Solid-State Circuits Conference, pp. 61-64, 2008.
[18] Jing Yang, T.L Naing, R.W Brodersen, “ A 1GS/s 6 bit 6.7 mW Successive Approximation ADC Using Asynchronous Processing,” IEEE Journal of solid-state Circuits, vol.45, no. 8, pp.1469-1478, 2010.
[19] S. Chuenarom, V. Tipsuwarnpron, “Application Techniques for High Performance ADC.” Proceedings of IEEE International Symposium on Communications and Information Technologies, pp. 749-752, 2006.
[20] Fang Xiang, V srinivasan, J wills, J. Granacki, J. LaCoss, J. Choma, “CMOS 12 bits 50kS/s Micropower SAR and Dual-Slope Hybrid ADC,” Proceedings of IEEE International Midwest Symposium on Circuits an Systems, pp. 180-183, 2009.
[21] Hyumgseok Kim, Junghan Lee, T. Copani, S. Bazarjani, S, B. Bakkaloglu, “ Adaptive Blocker Rejection Continuous-Time sigma-delta ADC for Mobile WiMAX Applications.” IEEE journal of Solid-State Circuits, vol. 44, no. 10, pp. 2766-2779, 2009.
[22] Yu-Chang Lien, “Low-Power High-Speed Flash Analog-to-Digital Converters.” Department of Electrical Engineering National Cheng Kung University Tainan, Taiwan, R.O.C. Thesis for Master of science, July, 2008.
[23] Chung Yung-hui, “Low-Power Analog-to-Digital Converters Design Techniques.” A Dissertation Submitted to Department of Electronics Engineering and Institute of Electronic National Chiao-Tung University in partial Fulfillment of the Requirements for the Degree of Doctor of philosophy in Electronics Engineering, July, 2010.
[24] Tsung-Yu Lai, “ A 9bit, 80MS/s Low Power Pipelined Analog to Digital Converter.” A Thesis Submitted to Department of Computer and Information Science College of Electrical Engineering and Computer Science National Chiao Tung University in partial Fulfillment of the Requirements of the degree of Master in Electronics Engineering, December, 2007.
[25] Huang Yi-Guei,” A Power and Area Optimum Flash Analog to Digital Conver.” Department of Electrical Engineering National Cheng Kung University Tainan, Taiwan, R.O.C. Thesis for Master of science, July, 2009.
[26] C. H. Chang, C. Y. Hsiao and C. Y. Yang, “A 1–GS/s CMOS 6-bit Flash ADC an Offset Calibrating Method,” VLSI Design, Automation and Test, 2008. VLSI-DAT 2008. IEEE International Symposium on Digital Object Identifier: 10.1109/VDAT.2008.4542455 Publication Year: 2008 , Page(s): 232 – 235.
[27] H. Y. Lee, I. H. Wang and S. I. Liu, “ A 7-BIT 400MS/s sub-ranging flash ADC in 0.18um CMOS,” SOC Conference, 2007 IEEE International Digital Object Identifier: 10.1109/SOCC.2007.4545415 Publication Year: 2007 , Page(s): 11 – 14.

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1. 于有慧。〈中國的大國外交〉,《中國大陸研究雜誌》,第42卷第3期,1999年,頁45-62。
2. 于有慧。〈中共外交政策走向與選擇〉,《問題與研究》,第43卷第1期,2004年,頁105-124。
3. 王友辰。〈中共對九0年代國際形式評估之探討〉,《中共研究雜誌》,第33卷第4期,1999年,頁74-85。
4. 方華。〈析中共領導人頻密訪歐與雙邊關係發展〉,《中共研究雜誌》,第38卷第8期,2004年,頁82-94。
5. 文馨。〈對中國威脅論之研析〉,《中共研究雜誌》,第29卷第8期,1995年,頁52-69。
6. 以理。〈中共『十七大』前政、經、軍、外交工作之探討〉,《中共研究雜誌》,第41卷第2期,2007年,頁4-15。
7. 吳建德。〈中共推動軍事外交戰略之研究〉,《中共研究雜誌》,第34卷第3期,2000年,頁82-97 。
8. 吳瑟致。《評中國和諧外交的內涵與影響》,中共研究雜誌,第41卷第1期,2007年,頁34-40。
9. 吳衛。〈中共近年對外軍事交流發展初探〉,《陸軍月刊》,第41卷第481期,1995年,頁39-53。
10. 李以珍。〈2007年中共外交」〉,《中共研究雜誌》,第42卷第2期,2008年,頁47-57。
11. 邱坤玄。〈結構現實主義與中共大國外交格局〉,《東亞季刊》,第30卷第3期,1999年,頁23-38。
12. 沈明室。〈中共十六大權力繼承與軍隊角色〉,《展望與探索》,第1卷第2期,2003,頁31-51。
13. 宋鎮照。〈中共與東南亞之政經關係與發展:回顧與前瞻〉,《東亞季刊》,第29卷第1期,1988年,頁51-62。
14. 林佳玲。〈中共參與國際聯合軍事演習作為探析〉,《中共研究雜誌》,第41卷第4期,2007年,頁95-107。
15. 林經緯。〈邁向軍事聯盟?探索中俄軍事合作的虛實〉,《中國大陸研究雜誌》,第50卷第3期,2007年,頁53-79。
 
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