臺灣博碩士論文加值系統

內容可定址記憶體擁有快速資料搜尋比對的優點，故現今已被廣泛使用在各種通訊網路、快取系統等應用上。然而，在進行資料搜尋比對的動作數量大且為平行比對，因此面積、功率消耗及可靠度已成為內容可定址記憶體最主要的問題。
預先計算的概念通常被使用在內容可定址記憶體上，使其可達到快速與減少功率消耗的特性。故在本篇論文中，我們探討三種基於內容可定址記憶體架構設計之預先計算的方法，並分析此三種預先計算方法的優點。首先，應用最高有效位元之內容可定址記憶體不需額外的記憶體面積。而伯格碼為等權的一種，故應用伯格碼概念可縮小內容可定址記憶體細胞之面積或將其應用至多值快閃內容可定址記憶體上可將資料搜尋比對次數降為一次。最後，為本研究所提出應用漢明碼概念來達到預先計算的方法，其擁有低功率消耗、面積小的檢查電路與可以進行資料錯誤更正的優點。利用本篇提出之新穎的漢明碼將可改善30%的功率消耗。
此外，在本篇論文中，我們也提出應用等權碼概念之多值快閃內容可定址記憶體使其擁有低成本與快速的特性。首先，應用等權碼定理使得多值快閃內容可定址記憶體的搜尋比對次數只需要一次，再者，我們利用伯格碼編碼可將儲存記憶體之電晶體個數大量地減少。在實驗部分，使用TSMC 0.18μm CMOS 1P6M製程，利用等權碼編碼方法做為設計基礎，模擬以快閃記憶體細胞為基礎的內容可定址記憶體架構。對於一個快閃內容可定址記憶體細胞在供應電壓為3.3V之下，資料搜尋的延遲時間大約為0.37ns。

Content addressable memory has the advantage of high-speed data searching, so it is widely used in communication network and cache system. However, owing to mass and parallel comparison, the area overhead, power dissipation and reliability are still the major issues for content addressable memory device.
Precomputation is usually applied in content addressable memory for predictive speedup and power disabling. In this paper, three efficient subspace codes are surveyed for precomputation based content addressable memory. The side benefits are also analyzed in the experiments. Form our evaluations the most significant bits concept does not need the extra-content addressable memory area overhead. Berger codes can be applied to hold the equal-weight property for cell reduction or searching-once. The proposed precomputation using Hamming codes can takes more benefits on low-power, small checkers and error correction. The novel Hamming codes is presented for improve the power consumption of 30%.
In this paper we also propose an equal-weigh codes multi-level cell flash content addressable memory with low-cost and high-speed features. Firstly applying the EWC theory the searching times can be reduced to once for MLC FCAM. Secondly we use the Berger codes to reduce the floating gate transistor count of the data memory circuitry. In the experimental result, the flash-based CAM based on equal-weigh codes design was implemented with the TSMC 0.18μm CMOS technology under 3.3V supply voltage. The Search-to-Match delay time of flash cell is about 0.37ns.

目錄

中文摘要 I
ABSTRACT II
誌謝 III
目錄 IV
圖目錄 VI
表目錄 VIII
第一章 緒論 1
1.1 研究背景 1
1.2 研究動機及目的 1
1.3 本論文架構編排 3
第二章 內容可定址記憶體的編碼概論 5
2.1 以預先計算為基礎的內容可定址記憶體 5
2.2 低功率預先計算內容可定址記憶體之合成 8
2.3 等權碼 11
2.3.1 等權碼概念 11
2.3.2 傳統伯格碼 12
2.3.3 伯格反相碼 13
第三章 三種編碼概念之預先計算內容可定址記憶體 15
3.1 提出三種編碼方式的参考文獻 15
3.2 提出新穎的編碼方式 18
第四章 快閃內容可定址記憶體的相關研究與技術 24
4.1 快閃記憶體結構及基礎原理 24
4.2 一顆電晶體之多階內容可定址記憶體 27
4.3 NAND型態之快閃內容可定址記憶體 28
第五章 應用等權碼觀念之多值快閃內容可定址記憶體架構 32
5.1 應用等權碼之多值快閃內容可定址記憶體 32
5.1.1 多值等權碼定理 32
5.1.2 應用多值等權碼定理之快閃內容可定址記憶體 34
5.2 快閃內容可定址記憶體細胞 36
5.2.1 成對地快閃內容可定址記憶體細胞設計 36
5.2.2 應用伯格碼編碼之成對地快閃內容可定址記憶體細胞架構 39
5.3 靜態式虛擬NMOS比對電路 40
5.4 應用等權碼概念之快閃內容可定址記憶體電路 41
第六章 多目的預先計算式內容可定址記憶體之分析 42
6.1 功率消耗之分析 42
6.2 資料儲存記憶體面積之分析 44
6.3其他特性之分析 46
第七章 快閃內容可定址記憶體的實驗結果與分析 48
7.1 快閃記憶體模型之設計 48
7.2 模擬結果 50
7.2.1 快閃記憶體模型之驗證 50
7.2.2 儲存記憶體模擬 51
7.2.3 應用等權碼概念之多值快閃內容可定址記憶體架構模擬 52
第八章 結論 53
參考文獻 55
作者簡歷 60

圖目錄
圖 1-1 預先計算的基本概念 2
圖 2-1 靜態式虛擬nMOS 字元比對電路 6
圖 2-2 (a)傳統內容可定址記憶體之資料儲存記憶體方塊圖
(b)預先計算為基礎之鍵值儲存記憶體方塊圖 7
圖 2-3 預先計算為基礎之靜態式虛擬nMOS比對電路 8
圖 2-4 預先計算為基礎之全平行內容可定址記憶體架構 8
圖 2-5 n位元Block-XOR方塊圖 10
圖 2-6 典型伯格碼(a)編碼器 (b)檢查器 12
圖 2-7 伯格反相碼(a)編碼器 (b)檢查器 14
圖 3-1 以預先計算為基礎之內容可定址記憶體細胞[21] 16
圖 3-2 最高有效位元示意圖 17
圖 3-3 應用最高有效位元之資料儲存記憶體方塊圖 18
圖 3-4 漢明碼系統示意圖 19
圖 3-5 漢明碼電路圖 22
圖 3-6 應用漢明碼概念之內容可定址記憶體方塊圖 23
圖 4-1 浮接閘電晶體剖面圖 25
圖 4-2 通道熱電子注入 25
圖 4-3 F-N穿隧 26
圖 4-4 快閃記憶體讀的動作 (a)讀出邏輯“0” (b)讀出邏輯“1” 26
圖 4-5 內容可地址記憶體之一字組的區塊動作比較 27
圖 4-6 多值內容可定址記憶體單元之電路 28
圖 4-7 符合線為NOR型態之NAND結構非揮發性內容可定址記憶體的電路架構 30
圖 4-7 符合線為NAND型態之NAND結構非揮發性內容可定址記憶體的電路架構 31
圖 5-1 比較值的補數與儲存值的總和用來當檢查器 34
圖 5-2 1T快閃內容可定址記憶體 36
圖 5-3 兩對快閃電晶體為一細胞之儲存記憶體架構 38
圖 5-4 應用伯格碼編碼之儲存記憶體架構 40
圖 5-5 靜態式虛擬nMOS字元比對電路設計 41
圖 5-6 應用等權碼概念之多階快閃內容可定址記憶體架構 41
圖 6-1 資料儲存方塊比對圖 44
圖 7-1 浮接閘電晶體之電子特性模型 48
圖 7-2 快閃記憶體細胞之模型 49
圖 7-3 Vg對Ids的特徵曲線圖 50
圖 7-4 快閃記憶體細胞動作曲線 51
圖 7-5 NOR-type 字元比對電路架構 51
圖 7-6 單一快閃記憶體細胞資料搜尋量測圖 52

表目錄
表 2-1 利用計數1之個數來代表特徵值的方式，相同特徵值之資料數目與平均機率 10
(a)文獻[7]，(b)文獻[13] 10
表 3-1 檢查位元之資料位元位置表 19
表 3-2 驗證位元之資料位元位置表 20
表 4-1 電壓對應之邏輯值 28
表 5-1 儲存記憶體之詳細邏輯值與電壓 35
表 5-2 儲存記憶體內每顆電晶體導通狀態 36
表 5-3 兩對快閃記憶體細胞之編碼表 39
表 7-1 快閃記憶體動作之電壓值 49
表 7-2 16階內容可定址記憶體的比較 52
表 7-3 搜尋次數 52

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