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研究生:劉隽宇
研究生(外文):Chun-Yu Liu
論文名稱:使用0.18 微米製程應用於無線通訊系統之射頻前端電路設計
論文名稱(外文):The front-end Circuits in 0.18 μm RF CMOS Process for Wireless Communication Systems
指導教授:翁若敏
指導教授(外文):Ro-Min Weng
學位類別:博士
校院名稱:國立東華大學
系所名稱:電機工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2010
畢業學年度:99
語文別:英文
論文頁數:118
中文關鍵詞:無線通訊系統射頻前端電路
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近幾年,無線通訊系統有很大的進步。而很多標準都是為了提供無線通訊系統,像是Bluetooth ,Wi-Fi,WiMAX (Worldwide Interoperability for Microwave Access),以及UWB (Ultra-Wideband)。這些標準都提供人類生活上的便利。

此篇論文實現了三個金氧半場效電晶體(MOSFET) 所設計的射頻積體子電路(RFIC),這些子電路都是使用台積電(TSMC)0.18 μm RF CMOS 製程。

首先,第一個電路是利用雜訊抵消架構的低雜訊放大器並應用於超寬頻系統中高頻段的部分。此電路的特點為將輸入訊號所遇到第一極的雜訊源經由兩條路徑來做抵銷的動作。此兩條路徑不但可以抵消輸入極雜訊亦可增加整體的增益值。此雜訊放大器整體架構是利用電流再利用所組成。以達到低功率的效果。此次實現的低雜訊放大器所操作的電壓為1.5 伏。功率消耗為10.7 毫瓦。操作頻率為6 到9 GHz。其輸入以及輸出的反射損耗都在-10 dB 以下。在操作頻率下,增益為2 到9.4 dB。在操作頻率為9.2 GHz 時,關於線性度的 IIP3 則為-13.34 dBm,雜訊指數為4.3 dB,晶片面積為0.91 mm2。此提出的低雜訊法大器的特點在於雜訊可以有效的抑制整個頻段。此電路在實現於晶片上時,因為製成的飄移以及輸出端的部分為增益電流相加與雜訊電流相減的情形,所以輸出頻寬匹配部分與模擬相差許多, 在輸出端加入獨立的輸出緩衝器,則可以使輸出匹配達到更好的效果。

接著為除數為2 的注入鎖定式的除頻器。此電路的特點是利用增加振幅的方式來增加鎖定頻寬的範圍。此方式以不增加電流路徑於整體架構中為設計條件下完成,因此不增加功率消耗,以達到低功率的效果。此次實現的注入鎖定式的除頻器所操作的電壓為1 伏。功率消耗為5.7 毫瓦。操作頻率為7.65 到7.85 GHz。鎖定時,在1MHz 的偏差頻率條件下,相位雜訊為從-122.2 dBc/Hz 到-130.68 dBc/Hz。晶片面積為0.52 mm2。此提出的注入鎖定式的除頻器的特點在於在低電壓操作下,也有低功率消耗的表現。如果在增加振幅的電路改用一般的放大器,雖然振幅可以有效的增加,但是功率消耗也會因此增加。所以功率消耗與範圍鎖定的頻率範圍對此架構而言是相互取捨。

最後為應用於5 到6 GHz WiMAX 系統並利用折疊架構的次諧波混頻器。此電路的特點是利用折疊架構,所以可以達到低於1 伏操作的效果。而且折疊架構亦可以使本地振盪訊號不直接影響射頻以及中頻訊號。利用次斜波架構可以使本地振盪訊號的操作頻率減半,所以可以減少本地振盪訊號對整體電路的影響。此次實現的低雜訊放大器所操作的電壓為0.8 伏。功率消耗為2.1 毫瓦。操作頻率為5 到6 GHz。其輸入反射損耗,包含射頻訊號端(RF signal stage) 或是本地振盪訊端(LO signal stage) 都在-10 dB 以下。其輸出的反射損耗,中頻訊號端(IF signal stage),亦在-10 dB 以下。在操作頻率下,增益為3.5 到5.2dB。相關於線性度的IIP3 則為-2.1 到-4.5 dBm。在6GHz 時,最小雜訊指數為14 dB. 晶片面積為1.13 mm2。此提出的次諧波混頻器的特點在於在低電壓操作下,也有低功率消耗的表現。因為使用的混波器為單端平衡是架構,而切換級輸入端為射頻訊號而非本地振盪器的輸出訊號,因此切換級輸入端的射頻訊號比起一般的混波器而言較大。

本論文所提出的射頻積體電路經量測與模擬之結果,可以適用於相關的通訊系統中。在未來將針對各電路整合,統整於單一通訊系統架構的接收器。
In the recent years, wireless communication systems are advanced. There are many standards, which are like Bluetooth, Wi-Fi, WiMAX (Worldwide Interoperability for Microwave Access), and UWB (Ultra-wideband), to provide wireless communication systems. Each of theses standards supplies the convenient for the people life.

In the dissertation, there are three RF CMOS sub-circuits presented. They are all designed and presented in TSMC 0.18 μm RF CMOS technology.

First, the noise-cancelling low noise amplifier (NC-LNA) for UWB Upperband systems is presented. The proposed LNA uses two path to cancel the noise source of the transistor in the first stage which is also the input stage. Because of the two paths, the gain can increase. The topology of the proposed LNA uses the current reused to decrease the current consumption and power consumption. The supply voltage of the proposed NC-LNA is 1.5 V and the power consumption is 10.7 mW. The operating frequency range is from 6 to 9.8 GHz. The input and output return loss are less than -10 dB. The gain is form 2 to 9.4 dB in the operating frequency range. The IIP3 is -13.34 dBm at operating 9.2 GHz. The noise figure is 4.3 dB. The chip area is 0.91 mm2. The proposed NC-LNA can decrease the noise in the operating frequency band, effectively. When realizing the NC-LNA on the chip, because of the process variation and the output stage, which increase the current gain and decreases the current noise, the measurement result and simulation result of the output return loss are different in the operating bandwidth. Adding an independent output buffer in the output stage, the output return loss has a better performance.

And then, the divide-by-two injection-locked frequency divider (ILFD) is presented. The proposed frequency divider uses increasing amplitude of input signal structure to increase frequency locked range. This structure does not need any other current paths, so it dose not increase power consumption. The supply voltage of proposed ILFD is 1 V and the power consumption is 5.7 mW. The operating frequency range is from 7.65 to 7.84 GHz. The phase noise is from -113.02 to -137.23 dBc/Hz at 1MHz offset in the locked stage.
The performance of lower phase noise is the locked situation. The chip area is 0.52 mm2. The proposed ILFD can achieve low power consumption with the low supply voltage. Using an amplifier replaces the proposed structure, although the swing of the input signal can increase, the power consumption is also increase. So it is the trade-off between the power consumption and the locked frequency range.

Finally, the sub-harmonic mixer (SH-mixer) with folding structure for 5∼6 GHz WiMAX systems is presented. The proposed mixer uses the folding structure to decrease the supply voltage, and the LO signal can not affect the RF and IF signals directly. The sub-harmonic structure, which is at the LO stage, makes the operating frequency of LO signals to be just half of the traditional structure. The supply voltage of proposed mixer is 0.8 V and the power consumption is 2.1 mW. The operating frequency range is from 5 to 6 GHz. The input return losses, which simulate from RF and LO input stage, are less than -10 dB. The output return loss, which simulates from IF output stage, is also less than -10 dB. The gain is form 3.5 to 5.2 dB in the operating frequency range. The IIP3, which is about linearity, is from -2.1 to -4.5 dBm at operating frequency range. The minimum noise figure is 14 dB at 6 GHz. The chip area is 1.13 mm2. The proposed SH-mixer can achieve low power consumption with the low supply voltage. Because the SH-mixer is the single balance structure, and the input of the switching stage is the RF signal not the LO signal. The power of the RF signal is bigger than other normal mixers.

From the simulation and measurement results of the proposed RF sub-circuits in this dissertation, they all accept for the related communication systems. In the future, all the proposed circuits may combine to become a receiver in the same RF communication system.
中文摘要i
Abstract iii
誌謝vii
1 Introduction 1
1.1 Motivation . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Thesis Organization . . . . . . . . . . . . . . . . . . 4
2 The Noise Cancelling LNA for UWB Upper-band Systems ......7
2.1 The Traditional Noise Cancelling LNA . . . . . . . .. . 8
2.2 The Proposed Noise Cancelling LNA . . . . . . ... . . . 9
2.3 The Analysis of the Proposed LNA . . . . . . . . . . . 9
2.3.1 The Noise Cancelling Analysis . . . . . . . .. . . . 11
2.3.2 The Voltage Gain Analysis . . . . . . . . .. . . . . 15
2.3.3 The Power Consumption Analysis . . . . . . ... . . . 18
2.4 Experimental Results and Discussion . . . . . . . . . 19
2.4.1 The Simulation Results of the Proposed LNA . ... . . 20
2.4.2 The Measurement Results of the Proposed LNA ...... . 25
2.5 Discussion . . . . . . . . . . . . . . . . . . . . . . 34
3 The Divide-by-two Injection-locked Frequency Divider ....37
3.1 The Traditional Injection-locked Divider . . . . . . . 37
3.2 The Proposed Divide-by-two Frequency Divider . . . . . 38
3.3 The Analysis of the Proposed Injection-locked Divider 39
3.4 Experimental Results and Discussion . . . . . . . . .. 44
3.4.1 The Simulation Results of the Proposed ILFD . . .. . 44
3.4.2 The Measurement Results of the Proposed ILFD . ..... 50
3.5 Discussion . . . . . . . . . . . . . . . . . . . . . . 63
4 The Sub-harmonic Mixer with Folding Structure for 5∼6 GHz WiMAX Systems............................................. 65
4.1 The Traditional Low Supply Voltage Design . . . . . . 66
4.2 The Sub-harmonic Structure Analysis . . . . . . .. . . 68
4.3 The Sub-harmonic Low Voltage Mixer for 5∼6 GHz WiMAX Systems . . . . . . . . . . . . . . . . . . . . . . . . . 69
4.3.1 The Single Balance Mixer . . . . . . . . . . . . . . 69
4.3.2 The Frequency Doubler Structure . . . . . . . .. . . 72
4.3.3 The Proposed Mixer . . . . . . . . . . . . . . . . . 73
4.4 The Simulation Results . . . . . . . . . . . . . . . . 74
4.5 Discussion . . . . . . . . . . . . . . . . . . . . . . 79
5 Conclusion and Future Work ..............................81
5.1 Conclusion . . . . . . . . . . . . . . . . . . . . . . 81
5.2 Future Work . . . . . . . . . . . . . . . . . . . . . 82
Bibliography ..............................................83
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