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研究生:顏靖人
研究生(外文):Ching-Jen Yen
論文名稱:應用於正交分頻多工超寬頻系統頻率合 成器之超低功耗壓控振盪器設計
論文名稱(外文):Design of Ultra-Low Power Voltage-controlled Oscillators for MB-OFDM UWB Frequency Synthesizers
指導教授:翁若敏
指導教授(外文):Ro-Min Weng
學位類別:碩士
校院名稱:國立東華大學
系所名稱:電機工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2011
畢業學年度:99
語文別:中文
論文頁數:81
中文關鍵詞:振盪器低功耗超寬頻
外文關鍵詞:Voltage-controlled OscillatorsLow PowerUWB
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由於科技的進步,近幾年無線通訊市場的蓬勃發展,將有線傳輸進化至無線傳輸,使得無線通訊系統變得相當重要,對於低功率、面積小、低相位雜訊等在射頻電路設計上是必須的要件,電壓控制振盪器(Voltage-controlled Oscillator;VCO)在通訊系統為非常重要之電路,在本論文中,將探討應用於正交分頻多工超寬頻系統頻率合成器之壓控振盪器之設計。
本論文晶片製程利用台灣積體電路製造公司(tsmc)0.18μm 1P6M CMOS製程技術實現,文中所提出兩個新型壓控振盪器電路頻率皆設定在8.4GHz,目的是為應用在改良之頻率合成器系統架構上,以低功耗為主要設計目標。第一顆晶片為8.4GHz之超低功率壓控振盪器,使用尾端耦合電容技術來降低偏壓電流以及低相位雜訊為主要設計考量,量測結果,此電路操作電壓為1.1V,功率消耗為4.4mW,相位雜訊為距離載波頻率1MHz處為-109dBc/Hz。第二顆晶片為8.4GHz之基極偏壓低功耗壓控振盪器設計,使用基極偏壓技術來降低操作電壓及使用虛電阻技術來降低電流來完成,此電路模擬結果,操作在低壓0.7V,功率消耗為1.3mW相位雜訊為距離載波頻率1MHz處為-114dBc/Hz。最後晶片並透過國家晶片系統中心進行量測。
提出之兩顆新型設計電路,第一個超低功率壓控振盪器量測中心頻率為6.02GHz,與當初模擬中心頻率有落差,消耗功率也因製程偏移與模擬有所影響。在第二個電路頻率同樣設計在8.4GHz,電路使用兩種設計概念,分別以降低操作電壓與降低電流來實現,相較第一個電路,此新型設計改變電晶體之臨界電壓,更能確保在低電壓0.7V操作,接著再使用虛電阻技術有效降低電流,使晶片能有更確保以低功率消耗來完成。
With the advance of technology and the rapid development of wireless communications market recent years, this makes the evolvement of a wire transmission into a wire transmission. The requirements of wireless communication system are low power, small size, low phase noise, etc. The voltage-controlled oscillators (VCOs) are one of the most important building blocks in the communication system, especially for RF circuit design this thesis was focused on the study and design of ultra-low power voltage-controlled oscillators for Multi-band Orthogonal frequency-division multiplexing ultra-wide band frequency synthesizers.
The chip of VCOs are fabricated by tsmc 0.18μm CMOS process. In this thesis, two proposed circuits are designed and implemented at the center frequency of 8.4GHz. The design purpose of VCO is to improve the application of the frequency synthesizer architecture. The goal of this thesis is to achieve low phase noise and low power consumption for frequency synthesizer applications. The first VCO was constructed based on the technique of control bias current and bottom-series coupling capacitor to achieve lower phase noise. The measured results show the power dissipation of the proposed core circuit is 4.4 mW at 1.1 V supply voltage. The phase noise of the proposed VCO is -109.1 dBc/Hz at 1 MHz offset frequency. The second VCO utilized the body bias technique to operate at low voltage. It can adjust the threshold voltage of MOS transistors to control power consumption. The differential bias currents at the fixed supply voltage can be decreased in comparison with those VCOs using double pseudo resistances in series with cross-coupled structures. The simulated results shows the core current is 1.9 mA at 0.7 V supply voltage. The phase noise of the proposed VCO is -114 dBc/Hz at 1 MHz offset frequency. Finally, the design chip was measured in national chip implementation center (CIC).
Two new circuit VCOs were proposed in this thesis. The first one is the ultra-low power VCO at 6.02GHz, with the original difference between the simulated results of center frequency, power consumption is also due to the process variation and simulation has been affected. The second circuit is also operated at 8.4GHz, the circuit utilized two design technique, to reduce the operating voltage and to lower the bias current. Compared to the first circuit, this new design adjusts the threshold voltage of MOS transistors to control power consumption. 0.7V low voltage operation is ensured, and the current is decreased by using double pseudo resistances. Finally the chip can achieve low power consumption to achieve.
誌謝 I
中文摘要 I
Abstract II
目錄 IV
圖目錄 VI
表目錄 VIII
第一章 序論 1
1.1 研究背景與動機 1
1.2 超寬頻系統簡介 2
1.3 超寬頻系統的特性 3
1.4超寬頻系統之頻帶規劃 4
1.5 論文架構 5
第二章 壓控振盪器介紹與原理分析 7
2.1 壓控振盪器介紹 7
2.2.1 振盪器模型 7
2.2.2 環型振盪器(Ring Oscillator) 8
2.2.3 電容電感諧振振盪器(LC-Tank Oscillator) 9
2.2.4 傳統LC-Tank振盪器簡介 12
2.2壓控振盪器的相位雜訊 14
2.2.1 相位雜訊的定義 14
2.2.2 相位雜訊對通訊系統的影響 16
2.2.3 相位雜訊分析-熱雜訊 18
2.2.4 相位雜訊分析-閃爍雜訊 20
2.2.5 相位雜訊分析-散彈雜訊 26
第三章 應用於超寬頻頻率合成器之低功耗壓控振盪器設計 31
3.1 超寬頻系統之頻率合成器架構介紹 31
3.2 8.4GHz之超低功耗壓控振盪器設計介紹 32
3.2.1 電路架構與設計 32
3.2.2 模擬環境 35
3.2.3 元件選擇 35
3.2.4 緩衝電路 36
3.2.5 模擬結果 39
3.2.6 電路佈局 44
3.2.7 晶片量測與結果討論 46
3.2 8.4GHz之基極偏壓低功耗壓控振盪器設計介紹 50
3.2.1 電路架構與設計 50
3.2.2 模擬環境 54
3.2.3 模擬結果 54
3.2.4 架構比較與模擬討論 58
3.2.5 電路佈局 61
3.2.6 晶片量測與模擬修正 62
第四章 結論與未來研究方向 65
4.1 結論 65
4.2 未來研究方向 66
參考文獻 67
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