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研究生:姚承汶
研究生(外文):Yao, Chengwen
論文名稱:即時多處理器嵌入式系統具工作遷移之DVS節能排程演算法
論文名稱(外文):Low-Power DVS Scheduling Algorithm with Task Migration for Real-Time Multi-Processsor Embedded Systems
指導教授:王煌城
指導教授(外文):Wang, Hwangcheng
口試委員:修丕承吳晉賢許孟超
口試日期:2011/07/18
學位類別:碩士
校院名稱:國立宜蘭大學
系所名稱:電子工程學系碩士班
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2011
畢業學年度:99
語文別:英文
論文頁數:47
中文關鍵詞:嵌入式系統工作排程多核心
外文關鍵詞:Embedded SystemsTask SchedulingMulti-Processor
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近年來嵌入式系統的方便性與移動性都有長足的進展,嵌入式系統上運算的需求急速的增加,在娛樂方面不管是遊戲或是影音的表現要求也越來越高,所以多核心成為嵌入式系統架構的趨勢,特別是在即時嵌入式系統上,而嵌入式系統朝多核心、多執行緒的趨勢發展,不但可以增加運算的效能也可降低系統的溫度。在這類系統中,如何延長待機與使用時間是迫切需要解決的問題。我們首先針對即時性系統的排程做研究,討論即時作業系統的排程條件--如何在即時性系統中排程以符合即時性條件。接下來對於DVS (Dynamic Voltage Scaling)的策略做研究,以減少系統功耗,包括其他研究排程策略的介紹,並提出新的排程演算法。在我們提出的演算法中除了執行順序上的安排,也考慮每個核心執行的速度與工作量,在執行階段,可以動態修改排程結果,平衡每個核心的工作量,讓系統可以更快以較低的速度工作,以達到節能效果;此外,我們也設法減少不必要的工作頻率切換以達到進一步的節能效果,最後我們套用真實的處理器功耗模型進行模擬,證實在很多的情況下都可以得到較現有方法更好的結果,不同的參數值對效能的影響也加以探討。
In recent years, portable devices and tablet PCs grow fast and become more convenient and mobile. Applications like multimedia, video and audio stream communications, and 3D movies become more pervasive than before. All these lead to the widespread use of multiprocessors in real-time embedded systems. However, the complex architecture and heavy computing demands in such systems increase power consumption. Therefore, how to extend the standby and usage time of the devices has become an important issue. In this thesis we propose a task scheduling algorithm in a real-time multi-processor system. We reduce the workload in high speed processors with the aid of task migration so that the entire system can switch to low speed as soon as it can in order to reduce power consumption. A distinctive feature is that actual execution time is used in the decision instead of worst-case execution time, which allows for more effective task migration and earlier transition to lower operation speed. We also analyze the overhead associated with DVS and suggest a strategy to avoid unjustified transitions between operation frequencies. Performance results based on realistic processor power consumption models are promising. Effects of parameter values on the performance are also examined and analyzed.
Chapter 1 Introduction
1.1. Motivation
1.2. Contributions
1.3. Thesis Organization
Chapter 2 Related Work
2.1. Dynamic Voltage Scaling
2.1.1. Dynamic Voltage Scaling Overhead
2.2. Multi-Processor Scheduling
Chapter 3 System Model and Proposed Scheduling Algorithm
3.1. System Model
3.2. The Proposed Algorithm
3.2.1. WATM for Task Allocation
3.2.2. WATM for DVS and Task Migration
3.3. Reduction of DVS Overhead
Chapter 4 Simulation Results
4.1. Normalized Energy
4.2. Number of Active Processors
4.3. DVS Overhead
Chapter 5 Conclusion and Future Research
5.1. Conclusion
5.2. Future Research
References

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