電子產品系統運作在高速時，可能產生時脈相位錯離之現象，傳統單一相位的輸出電路無法提供系統需求更多的彈性，多相位電路日愈重要也適用於很多種應用上，可是多相位會因外在環境因素，導致相位間有所偏移，會大大地影響系統效能與晶片可靠度，我們利用多相位延遲鎖定迴路來克服此問題。

我們使用數位至電壓轉換器、重覆利用連續逼近控制單元及電壓控制延遲線，以此概念設計的多相位延遲鎖定迴路。簡化傳統連續逼近控制電路，利用重覆操作的觀念，來達到節省面積及成本的目的，此電路實現於台積電0.18μm CMOS製程，佈局電路的核心面積為217.8 * 332.3μm²，採用28Pin之ESD保護電路，整體晶片面積為998 * 1018μm²，工作頻率範圍為100MHz到165MHz，RMS jitter為29ps、Pk-Pk jitter為174ps。

除此之外，為改善因製程、電壓、溫度所造成的相位偏移，提出一個改良型校準技術，改良了以往連續式的校準，實際電路上新相位產生出來還有些不穩定，等相位穩定後再進行校準動作，先校準奇數相位後再校準偶數相位，稱為跳耀式循序校準，提高其校準的速度和精確度。此電路實現於台積電0.18μm CMOS製程，佈局電路的核心面積為469.4 * 471.7μm²，採用28Pin之ESD保護電路，整體晶片面積為978* 983μm²，工作頻率範圍為100MHz到165MHz，RMS jitter為28ps、Pk-Pk jitter為145ps。

The electronic products system is working on high speed clock rate which the clock phase skew may arise. The traditional single-phase output circuit can’t provide flexible system requirements. The multi-phase circuit is important and applicable to applications. But, the multi-phase circuit have phase offset due to external environment factors. It will greatly affect system performance and chip’s reliability. Therefore, we propose a self-calibrated multiphase delay-locked loop with reuse-SAR.

We use the digital-to-voltage converter (DVC), reuse successive approximation register control circuit and the voltage control delay line to design multi-phase delay-locked loop. We simplify the traditional successive approximation register control circuits, using the repeated operations to achieve. It can reduce the hardware space and cost. The chip has been implemented in TSMC 0.18μm. The core area of the chip is 217.8 * 332.3μm² and the total area is 998 * 1018μm² including 28 ESD pins. Operation frequency is 100MHz to 165MHz. The RMS jitter is 29ps and Pk-Pk jitter is 174ps.

In addition, this thesis presents a modified calibration technique in order to improve the phase offset caused by process, voltage, temperature. We improve the traditionally continuous calibration algorithm which it causes the phase instability because of phase stability after the calibration operation. We propose a calibration algorithm with odd phases, then with even phases which is called the sequential jumping method. It improves speed and accuracy of the calibration. The chip has been implemented in TSMC 0.18μm. The core area of the chip is 469.4 * 471.7μm² and the total area is 978* 983μm² including 28 ESD pins. Operation frequency is 100MHz to 165MHz. The RMS jitter is 28ps and Pk-Pk jitter is 145ps.

摘要 ------------------------------------------------------ I
Abstract ------------------------------------------------------ II
誌謝 ------------------------------------------------------ IV
目錄 ------------------------------------------------------ V
圖目錄 ------------------------------------------------------ VIII
表目錄 ------------------------------------------------------ XIV
第一章 緒論 -------------------------------------------------- 1
1.1 研究動機 ----------------------------------------------- 1
1.2 文獻探討 ----------------------------------------------- 2
1.2.1 延遲鎖定迴路分類 ---------------------------------- 2
1.2.2 延遲鎖定迴路架構簡介 ------------------------------ 4
1.2.3 延遲鎖定迴路發展趨勢 ------------------------------ 10
1.2.4 校準技術 ------------------------------------------ 11
1.3 研究重點 ----------------------------------------------- 12
1.4 論文架構 ----------------------------------------------- 12
第二章 多相位重覆利用連續逼近暫存器延遲鎖定迴路 -------------- 13
2.1 延遲鎖定迴路簡介 --------------------------------------- 13
2.2 電路架構與設計原理 ------------------------------------- 16
2.3 電路設計與模擬 ----------------------------------------- 18
2.3.1 相位偵測器(Phase Detector) --------------------------- 18
2.3.2 重覆利用連續逼近暫存器電路(Reuse SAR) ------------- 12
2.3.3 數位至電壓轉換器(DVC) ---------------------------- 26
2.3.4 電壓控制延遲線(VCDL) ----------------------------- 34
2.3.5 全電路模擬 ---------------------------------------- 40
2.4 電路佈局與佈局模擬 ------------------------------------ 46
2.5 晶片量測 ---------------------------------------------- 55
第三章 改良型校準電路 ---------------------------------------- 61
3.1 多相位輸出偏移現象介紹 --------------------------------- 61
3.2 各種校準技術介紹 --------------------------------------- 63
3.2.1 連續循序相位調整校準技術 -------------------------- 63
3.2.2 平行相位調整校準技術 ------------------------------ 65
3.2.3 遞迴校位調整校準技術 ------------------------------ 66
3.3 改良型校準設計 ---------------------------------------- 68
3.3.1 設計原理 ------------------------------------------ 68
3.3.2 電路架構 ------------------------------------------ 71
3.4 電路設計與模擬 ----------------------------------------- 72
3.4.1 相位偵測器(Phase Detector) --------------------------- 72
3.4.2 內插器(Interpolator) --------------------------------- 74
3.4.3 上下數計數器(Up/Down Counter) --------------------- 77
3.4.4 延遲線(Delay Line) ---------------------------------- 79
3.4.5 全電路模擬 ---------------------------------------- 82
3.5 電路佈局與佈局模擬 ------------------------------------- 86
3.6 晶片量測 ----------------------------------------------- 95
第四章 校準技術使用MATLAB模擬 ----------------------------- 107
第五章 結論與未來研究方向 ------------------------------------ 115
5.1 結論 ------------------------------------------------- 115
5.2 未來研究方向 ----------------------------------------- 116
參考文獻 ----------------------------------------------------- 117

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