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研究生:王子祥
研究生(外文):Tzu-Hsiang Wang
論文名稱:多相位自我校準之重複逼近暫存器延遲鎖定迴路
論文名稱(外文):A Self - Calibrated Multiphase Delay - Locked Loop with Reuse SAR
指導教授:陳寶龍陳寶龍引用關係
指導教授(外文):Pao-Lung Chen
學位類別:碩士
校院名稱:國立高雄第一科技大學
系所名稱:電腦與通訊工程研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2011
畢業學年度:99
語文別:中文
論文頁數:138
中文關鍵詞:多相位延遲鎖定迴路校準技術
外文關鍵詞:DLLCalibration TechnologyMultiphase
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電子產品系統運作在高速時,可能產生時脈相位錯離之現象,傳統單一相位的輸出電路無法提供系統需求更多的彈性,多相位電路日愈重要也適用於很多種應用上,可是多相位會因外在環境因素,導致相位間有所偏移,會大大地影響系統效能與晶片可靠度,我們利用多相位延遲鎖定迴路來克服此問題。

我們使用數位至電壓轉換器、重覆利用連續逼近控制單元及電壓控制延遲線,以此概念設計的多相位延遲鎖定迴路。簡化傳統連續逼近控制電路,利用重覆操作的觀念,來達到節省面積及成本的目的,此電路實現於台積電0.18μm CMOS製程,佈局電路的核心面積為217.8 * 332.3μm²,採用28Pin之ESD保護電路,整體晶片面積為998 * 1018μm²,工作頻率範圍為100MHz到165MHz,RMS jitter為29ps、Pk-Pk jitter為174ps。

除此之外,為改善因製程、電壓、溫度所造成的相位偏移,提出一個改良型校準技術,改良了以往連續式的校準,實際電路上新相位產生出來還有些不穩定,等相位穩定後再進行校準動作,先校準奇數相位後再校準偶數相位,稱為跳耀式循序校準,提高其校準的速度和精確度。此電路實現於台積電0.18μm CMOS製程,佈局電路的核心面積為469.4 * 471.7μm²,採用28Pin之ESD保護電路,整體晶片面積為978* 983μm²,工作頻率範圍為100MHz到165MHz,RMS jitter為28ps、Pk-Pk jitter為145ps。
The electronic products system is working on high speed clock rate which the clock phase skew may arise. The traditional single-phase output circuit can’t provide flexible system requirements. The multi-phase circuit is important and applicable to applications. But, the multi-phase circuit have phase offset due to external environment factors. It will greatly affect system performance and chip’s reliability. Therefore, we propose a self-calibrated multiphase delay-locked loop with reuse-SAR.

We use the digital-to-voltage converter (DVC), reuse successive approximation register control circuit and the voltage control delay line to design multi-phase delay-locked loop. We simplify the traditional successive approximation register control circuits, using the repeated operations to achieve. It can reduce the hardware space and cost. The chip has been implemented in TSMC 0.18μm. The core area of the chip is 217.8 * 332.3μm² and the total area is 998 * 1018μm² including 28 ESD pins. Operation frequency is 100MHz to 165MHz. The RMS jitter is 29ps and Pk-Pk jitter is 174ps.

In addition, this thesis presents a modified calibration technique in order to improve the phase offset caused by process, voltage, temperature. We improve the traditionally continuous calibration algorithm which it causes the phase instability because of phase stability after the calibration operation. We propose a calibration algorithm with odd phases, then with even phases which is called the sequential jumping method. It improves speed and accuracy of the calibration. The chip has been implemented in TSMC 0.18μm. The core area of the chip is 469.4 * 471.7μm² and the total area is 978* 983μm² including 28 ESD pins. Operation frequency is 100MHz to 165MHz. The RMS jitter is 28ps and Pk-Pk jitter is 145ps.
摘要 ------------------------------------------------------ I
Abstract ------------------------------------------------------ II
誌謝 ------------------------------------------------------ IV
目錄 ------------------------------------------------------ V
圖目錄 ------------------------------------------------------ VIII
表目錄 ------------------------------------------------------ XIV
第一章 緒論 -------------------------------------------------- 1
1.1 研究動機 ----------------------------------------------- 1
1.2 文獻探討 ----------------------------------------------- 2
1.2.1 延遲鎖定迴路分類 ---------------------------------- 2
1.2.2 延遲鎖定迴路架構簡介 ------------------------------ 4
1.2.3 延遲鎖定迴路發展趨勢 ------------------------------ 10
1.2.4 校準技術 ------------------------------------------ 11
1.3 研究重點 ----------------------------------------------- 12
1.4 論文架構 ----------------------------------------------- 12
第二章 多相位重覆利用連續逼近暫存器延遲鎖定迴路 -------------- 13
2.1 延遲鎖定迴路簡介 --------------------------------------- 13
2.2 電路架構與設計原理 ------------------------------------- 16
2.3 電路設計與模擬 ----------------------------------------- 18
2.3.1 相位偵測器(Phase Detector) --------------------------- 18
2.3.2 重覆利用連續逼近暫存器電路(Reuse SAR) ------------- 12
2.3.3 數位至電壓轉換器(DVC) ---------------------------- 26
2.3.4 電壓控制延遲線(VCDL) ----------------------------- 34
2.3.5 全電路模擬 ---------------------------------------- 40
2.4 電路佈局與佈局模擬 ------------------------------------ 46
2.5 晶片量測 ---------------------------------------------- 55
第三章 改良型校準電路 ---------------------------------------- 61
3.1 多相位輸出偏移現象介紹 --------------------------------- 61
3.2 各種校準技術介紹 --------------------------------------- 63
3.2.1 連續循序相位調整校準技術 -------------------------- 63
3.2.2 平行相位調整校準技術 ------------------------------ 65
3.2.3 遞迴校位調整校準技術 ------------------------------ 66
3.3 改良型校準設計 ---------------------------------------- 68
3.3.1 設計原理 ------------------------------------------ 68
3.3.2 電路架構 ------------------------------------------ 71
3.4 電路設計與模擬 ----------------------------------------- 72
3.4.1 相位偵測器(Phase Detector) --------------------------- 72
3.4.2 內插器(Interpolator) --------------------------------- 74
3.4.3 上下數計數器(Up/Down Counter) --------------------- 77
3.4.4 延遲線(Delay Line) ---------------------------------- 79
3.4.5 全電路模擬 ---------------------------------------- 82
3.5 電路佈局與佈局模擬 ------------------------------------- 86
3.6 晶片量測 ----------------------------------------------- 95
第四章 校準技術使用MATLAB模擬 ----------------------------- 107
第五章 結論與未來研究方向 ------------------------------------ 115
5.1 結論 ------------------------------------------------- 115
5.2 未來研究方向 ----------------------------------------- 116
參考文獻 ----------------------------------------------------- 117
[1]T. Saeki, Y. Nakaoka, M. Fujita, A. Tanaka, K. Nagata, K. Sakakibara, T. Matano, Y. Hoshino, K. Miyano, S. Isa, S. Nakazawa, E. Kakehashi, J. M. Drynan, M. Komuro, T. Fukase, H. Iwasaki, M. Takenaka, J. Sekine, M. Igeta, N. Nakanishi, T. Itani, I. Yoshida, K. Yoshino, S. Hashimoto, T. Yoshii, M. Ichinose, T. Imura, M. Uziie, S. Kikuchi, K. Koyama, Y. Fukuzo, T. Okuda, “A 2.5-ns clock access, 250-MHz, 256-Mb SDRAM with synchronous mirror delay,” IEEE Journal of Solid-State Circuits, vol. 31, pp. 1656-`668, Nov. 1996.
[2]Y. Okajima, M. Taguchi, M. Yanagawa, K. Nishimura, and O. Hamada, “Digital delay locked loop and design technique for high-speed synchronous interface,” IEICE Trans. Electron., vol. E79-C, no. 6, pp. 798-807, June 1996.
[3]A. Hatakeyama, H. Mochizuki, T. Aikawa, M. Takita, Y. Ishii, H. Tsuboi, S.-Y. Fujioka, S. Yamaguchi, M. Koga, Y. Serizawa, K. Nishimura, K. Kawabata, Y. Okajima, M. Kawano, H. Kojima, K. Mizutani, T. Anezaki, M. Hasegawa, and M. Taguchi, “A 256-Mb SDRAM using a register-controlled digital DLL,” IEEE Journal of Solid-State Circuits, vol. 32, pp. 1728-1734, Nov. 1997.
[4]F. Lin, J. Miller, A. Schoenfeld, M. Ma, and R. J. Baker, “A register-controlled symmetrical DLL for double-data-rate DRAM,” IEEE Journal of Solid-State Circuits, vol. 34, pp. 565-568, Apr. 1999.
[5]H. Sutoh, K. Yamakoshi, and M. Ino, “Circuit technique for skew-free clock distribution,” in IEEE Custom Integrated Circuits Conf., 1995, pp. 163-166.
[6]Bum-Sik, and Lee-Sup Kim, “ A Low Power 100MHz All Digital Delay-Locked Loop,” IEEE International symposium on circuits and Systems, 1997, pp1820-1823
[7]H. Sutoh and K. Yamakoshi, “A clock distribution technique with an automatic skew compensation circuit,” IEICE Trans. Electron, vol. E81-C, no. 2, pp. 277-283, Feb. 1998.
[8]Chorng-Sii Hwang, Wang-Chih Chung, Chih-Yong Wang, Hen-Wai Tsao, Shen-Iuan Liu,” A 2V Clock Synchornizer using Digital Delay-Locked Loop,” The Second IEEE Asia Pacific Conference on ASICs, pp. 91-94, Aug. 2000.
[9]Guang-Kaai Dehng, June-Ming Hsu, Ching-Yuan Yang, and Shen-Iuan Liu, “Clock-Deskew Buffer Using a SAR-Controlled Delay-Locked Loop,” IEEE Journal of Solid-State Circuits, vol. 35, pp. 1128-1136, Aug. 2000.
[10]M. Miyazaki and K. Ishibashi, “A 3-cycle lock time delay-locked loop with a parallel phase detector for low power mobile systems,” The First IEEE Asia Pacific Conference on ASICs, pp. 396-399, Aug. 1999.
[11]Takanori Saeki, Koichiro Minami, Hiroshi Yoshida, and Hisamitsu Suzuki, ”A Direct-Skew-Detect Synchronous Mirror Delay for Application-Specific Integrated Circuits,” IEEE Custom Integrated Circuits Conference, pp. 511-514, 1998.
[12]Bum-Sik, and Lee-Sup Kim, “100MHz all-digital delay-locked loop for low power application,” Electronics Letters, pp. 1739-1740, 1998.
[13]Daeyun Shim; Dong-Yun Lee; Sanghun Jung; Chang-Hyun Kim; Wonchan Kim, “An analog synchronous mirror delay for high-speed DRAM application,” IEEE Journal of Solid-State Circuits, vol. 34, pp. 484-493, Apr. 1999.
[14]R.-J. Yang and S.-I. Liu ,“A 40–550 MHz Harmonic-Free All-Digital Delay-Locked Loop Using a Variable SAR Algorithm,” IEEE Journal of Solid-State Circuits, vol. 42, pp. 361-373, Feb. 2007.
[15]Bruno W. Garlepp, Kevin S. Donnelly, Jun Kim, Pak S. Chau, Jared L. Zerbe, Charles Huang, Chanh V. Tran, Clemenz L. Portmann, Donald Stark, Yiu-Fai Chan, Thomas H. Lee, and Mark A. Horowitz, “A Portable Digital DLL Architecture for CMOS Interface Circuits,” Symposium on VLSI Circuits Digest of Technical Papers, pp. 214-215, 1998.
[16]Kuo-Hsing Cheng, Yu-Lung Lo, “A Fast-Lock Wide-Range Delay-Locked Loop Using Frequency-Range Selector for Multiphase Clock Generator,” IEEE Trans. Circuits System II, vol. 54, pp. 561-565, July 2007.
[17]C.-C. Chung and C.-Y. Lee, “An all-digital phase-locked loop for high-speed clock generation,” IEEE Journal of Solid-State Circuits, vol. 38, pp. 347–351, Feb. 2003.
[18]C.-C. Chung and C.-Y. Lee, “A new DLL-based approach for all-digital multiphase clock generation,” IEEE Journal of Solid-State Circuits, vol. 39, no.3, pp. 469-475, Mar. 2004.
[19]Abdellatif Bellaouar and Mohamed I. Elmasry, “Low-Power Digital VLSI Design Circuits and Systems,” Kluwer Academic Publishers.
[20]S.-I. Liu, J.-H. Lee and H.-W. Tsao, “Low-Power Clock-Deskew Buffer for High-Speed Digital Circuit,” IEEE Journal of Solid-State Circuits, vol. 34, no.4, pp. 5543-5558, Apr. 1999.
[21]Terng-Yin Hsu, Terng-Ren Hsu, Chung-Cheng Wang, Yi-Chuan Liu, and Chen-Yi Lee, “Design of a Wide-Band Frequency Synthesizer Based on TDC and DVC Techniques,” IEEE Journal of Solid-State Circuits, vol.37, pp. 1244-1255 ,Oct. 2002.
[22]Chung-Cheng Wang, Chen-Yi Lee“A Digital Frequency Synthesizer HDL Generator for SOC Design,”國立交通大學,電子工程學系,電子研究所碩士班,碩士論文,中華民國八十九年六月.
[23]Yi-Chuan Liu, Chen-Yi Lee,“The Study of Wideband Digital Frequency Synthesizer (DFS) and its Applications,”國立交通大學,電子工程學系,電子研究所碩士班,碩士論文,中華民國九十年六月.
[24]Tsung-Hsiang Lin, “A Digital Controlled Multi-Phase Delay Locked Loop with Calibration Technique,” 國立高雄第一科技大學, 電腦與通訊工程系, 電腦與通訊研究所碩士班, 碩士論文, 中華民國九十八年六月.
[25]Pao-Lung Chen, Chun-Fu Liu, Tsung-Hsiang Lin, “A Multiphase Digital Controlled Oscillator with DVC Technique,” SASIMI, pp. 473–476, Mar. 2009.
[26]J. Maneatis, “Low-Jitter Process-Independent DLL and PLL Base on self-Biased Techniques,” IEEE Journal of Solid-State Circuits, vol.31, pp. 1723-1732, Nov. 1996.
[27]S.-K. Kao, B.-J. Chen and S.-I. Liu, "A 62.5-625MHz anti-reset all-digital delay-locked loop," IEEE Transactions on Circuits and Systems, vol. 54, no. 7, pp. 566-570, July 2007.
[28]Hsiang-Hui Chang, Jung-Yu Chang, Chun-Yi Kuo and Shen-Iuan Liu, “A 0.7-2GHz self-calibrated multiphase delay-locked loop,” IEEE Journal of Solid-State Circuits, vol. 41, pp.1051-1061, May 2006.
[29]C. H. Park, O. Kim, and B. Kim, “A 1.8-GHz self-calibrated phase locked loop with precise I/Q matching,” IEEE Journal of Solid-State Circuits, vol. 36, pp. 777-783, May 2001.
[30]S. H. Wang et al., “A 5-GHz band I/Q clock generator using a self-calibration technique,” 28th European Solid-State Circuits Conference, pp. 807-810, Sep. 2002.
[31]R. E. Best, phase-Locked Loops: Theory, Design and Applications, 2nd ed. New York: McGraw-Hill, 1993.
[32]L. Wu and W. C. Black, Jr., “A low-jitter skew-calibrated multi-phase clock generator for tome-interleaved application,” in International Solid-State Circuits Conference, pp. 396-399, Feb. 2001.
[33]陳寶龍、林琮翔、劉俊甫, “一種改良型多相位校準技術,”高科大電機資訊學院2008 年師生研發成果研討會, 高雄, pp. 84-89, May 2008.
[34]A. Momtaz, C. Jun, M. Caresosa, A. Hairapetian, D. Chung, K. Vakilian, M. Green, T. Wee-Guan, J. Keh-Chee, I. Fujimori, and C. Yijun, “A fully integrated SONET OC-48 transceiver in standard CMOS,” IEEE Journal of Solid-State Circuits, vol. 36, pp. 1964-1973, Dec. 2001.
[35]劉深淵 , 楊清淵著“鎖相迴路”滄海書局 , 95年11月初版.
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