本論文提出運用預失真技術抑制量化雜訊之發射機，本研究是利用數位預失真技術將基頻調制訊號進行預失真，在進行正交調制時與運用差異積分調制器(DSM，Delta-Sigma Modulator)之分數式頻率合成器的量化雜訊做抵銷，達到相位誤差補償並降低量化雜訊所造成之相位雜訊，研究結果其使用二階差異積分調制器並且預失真開啟時，相位雜訊表現可在迴路頻寬內降低6dB。

CMOS正交電壓控制振盪器設計部分，本研究使用TSMC 0.18um CMOS製程來設計5 GHz正交電壓控制振盪器，振盪器採並聯耦合架構，並將其振盪器晶片整合成直接升頻式發射機，並量測其調制品質。

This thesis presents the use of pre-distortion techniques to suppress quantization noise of the transmitter, this study is the use of digital pre-distortion technology baseband modulation signal pre-distortion, making use of orthogonal modulation with the Delta-Sigma Modulator (DSM) of the fractional quantization noise frequency synthesizer to do offset, phase error compensation and to reduce the quantization noise caused by the phase noise, the results of its second-order DSM pre-distortion is turned on, the phase noise performance within the loop bandwidth can be reduced 6dB.

CMOS quadrature voltage-controlled oscillator (QVCO) design part of this study using TSMC 0.18um CMOS process to design a 5 GHz QVCO, coupled oscillators to adopt parallel architecture, and integrated into the chip directly to the oscillator frequency transmitter and measuring the modulation quality.

第一章 緒論 1
1.1簡介 1
1.2章節規劃 6
第二章 運用差異積分調制器之分數式頻率合成器設計 7
2.1 整數式與分數式頻率合成器 7
2.1.1 整數式頻率合成器 7
2.1.2 分數式頻率合成器 9
2.2 運用差異積分調制器之分數式頻率合成器 11
2.2.1 差異積分調制器原理與架構 11
2.2.2 設計與模擬結果 15
2.2.3 量測結果 19
第三章 運用預失真技術抑制量化雜訊之發射機設計 22
3.1 架構簡介 22
3.2 預失真基頻數位電路單元設計 26
3.2.1 升餘弦濾波器 26
3.2.2 半頻帶濾波器 27
3.2.3 直角座標與極座標轉換單元 28
3.2.4 數位預失真器 29
3.2.5 數位類比轉換模組 30
3.3預失真訊號量測 31
3.3.1 預失真器關閉時之I、Q訊號量測結果 31
3.3.2 預失真器開啟時之I、Q訊號量測結果 33
3.4 系統量測設置 35
3.5 預失真技術抑制量化雜訊之發射機整合量測結果 36
第四章5.2 GHz 正交電壓控制振盪器CMOS晶片設計 44
4.1 簡介 44
4.2 電壓控制振盪器原理 46
4.3 正交電壓控制振盪器原理與架構 48
4.4 5.2 GHz CMOS正交電壓控制振盪器 51
4.4.1 設計與模擬結果 51
4.4.2 正交電壓控制振盪器量測結果 53
4.4.3 正交電壓控制振盪器整合鎖相迴路量測 58
4.4.4 正交電壓控制振盪器整合發射機量測 60
第五章 結論 63
參考文獻 64

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