臺灣博碩士論文加值系統

本論文以半導體模擬方式分析具有兩種單原子層摻雜與三種雙原子層摻雜分佈之磷化銦鎵/砷化鎵高電子遷移率場效電晶體，並分別進行比較。
首先，為了將載子有效的侷限在砷化鎵通道層中以減少閘極漏電流，採用了具有相當的導電帶不連續值磷化銦鎵/砷化鎵材料系統。且因閘極下方的磷化銦鎵層為大能隙且未摻雜，因而具有良好的蕭特基接觸，可得到大的閘極電壓操作範圍。
在兩種單原子層摻雜分佈的電晶體中，A元件及B元件分別為上、下層單原子層摻雜(n+ = 5 × 1012 cm-2)結構。模擬結果顯示，A元件與B元件之最大轉導值分別為164.28、107.4 mS/mm，最大汲極輸出電流分別為202、218.96 mA/mm，而閘極導通電壓分別可達1.04、1.09 V，臨界電壓分別為 -0.48、-2.044 V，輸出電導分別為1.116、0.789 mS/mm，單位電流增益截止頻率分別為12、6.5 GHz以及最大震盪頻率分別為45、17 GHz。值得注意的是，在低汲-源極電壓時所產生的曲膝效應。由於閘極空乏只發生在閘極金屬正下方區域，導致通道中對應閘極金屬的範圍，其二維電子氣濃度將比對應間隔區的範圍相對較低。因此，當載子在通道中傳輸時會面臨一個電位能障。然而，在大汲-源極電壓時，其區域電位能障下降，這將使載子從源極到汲極的傳輸變得容易，此時汲極電流將會迅速增加。
在三種雙重原子層摻雜分佈的電晶體中，其C元件為上、下層單原子摻雜濃度都是2.5 × 1012 cm-2的結構；D元件為上層單原子摻雜濃度1 × 1012 cm-2和下層單原子摻雜濃度4 × 1012 cm-2的結構；E元件為上層單原子摻雜濃度4 × 1012 cm-2和下層單原子摻雜濃度1 × 1012 cm-2的結構。模擬結果顯示，C元件、D元件和E元件之最大汲極飽和電流依序為268.589、279.277、283.188 mA/mm，臨界電壓依序為 -1.275、-1.736、-0.791 V，且最大轉導值依序為163、150.63、213.6 mS/mm。而電導值1.206、1.142、1.628 mS/mm，依序為閘極導通電壓依序為1.0487、1.063、1.042 V，單位電流增益截止頻率分別為9.5、8、12 GHz以及最大震盪頻率分別為42、25、55 GHz。此外，這些元件所顯示的優異特性，可應用於訊號放大器及高頻微波電路中。

In this thesis, we analyze and compare the characteristics of the two kind of InGaP/GaAs single delta-doped HEMTs and the three kind of InGaP/GaAs double delta-doped HEMTs.
Due to the considerable conductance-band discontinuity at InGaP/GaAs heterojunction, it can provide good carrier confinement in the channel layers and reduce gate leakage currents. In addition, because the gate barrier layer is undoped and large band gap, it has good Schottky characteristics to enhance the gate turn-on voltage and extend the gate operation region. In order to further increase the breakdown voltage and reduce leakage current, the delta-doped carriers supplied layer below the undoped gate layer is employed in the studied HEMTs.
Simulated results exhibit that the gate turn-on voltage up to 1.04 (1.09) V, the output conductance is 1.116 (0.789) mS/mm, the extrinsic transconductance is 164.28 (107.4) mS/mm, the maximum saturation output current density approximates 202 (218.96) mA/mm, the threshold voltage is -0.48 (-2.044) V, the unity current gain cut-off frequency is 12 (6.5) GHz, and maximum oscillation frequency is 45 (17) GHz for the single delta-doped HEMT with upper (lower) delta-doped sheet. Clearly, the lower delta-doped structure has higher gate turn-on voltage, lower conductance, higher saturation output current, larger magnitude of threshold voltage, and wider gate operation region. But, it has relatively lower transconductance and worse high-frequency characteristics. Furthermore, it is worthy to note that a considerable knee effect is observed at low drain-to-source voltage. There is a higher 2DEG concentration in the two spacer region than the gate region because the gate depletion only occurs below the gate metal. Thus, the carrier transportation along the 2DEG channel will face a potential barrier in the region below the gate metal at relatively small drain-to-source voltage. However, at large drain-to-source voltage the potential barrier is lower and the carriers easily transport along 2DEG channel from source to drain region. In this condition, the drain current will rapidly increase.
As considering the double delta-doped HEMTs, the top and bottom delta-doped concentrations are of 2.5 × 1012 and 2.5 × 1012 cm-2 for the device C, respectively. Similar to the device C, the concentrations of top and bottom delta-doped supplied layers are of 1 × 1012 (4 × 1012) cm-2 and 4 × 1012 (1 × 1012) cm-2, for the device D (device E). The simulation results show the gate turn-on voltages up to 1.0487, 1.063, and 1.0424 V for the devices C, D, and E, respectively. The next simulation results show the conductance are of 1.206, 1.142, 1.628 mS/mm for the devices C, D, and E, respectively. The next simulation results show the extrinsic transconductance of 163, 150.63, and 213.6 mS/mm for the devices C, D, and E, respectively. The next simulation results show the maximum saturation current densities of devices C, D, E are 268.589, 279.277, and 283.188 mA/mm, respectively. The next simulation results show the threshold voltages are of -1.275, -1.736, and -0.791 V for the devices C, D, and E, respectively. The next simulation results show the ft (fmax) are 9.5 (42), 8 (25), and 12 (55) GHz for the devices C, D, and E, respectively. Obviously, the device E has the highest saturation output current, the largest transconductance, and the best frequency characteristics. However, it has the lowest gate turn-on voltage, the largest conductance, the smallest magnitude threshold voltage, and the narrowest gate operation region. These characteristics associated with delta-doped concentration vary. Furthermore, we can observe from these data that the double delta-doped supplied layers structure can more effectively improve the output saturation current, transconductance and frequency characteristics. The excellent device performance provides a promise for signal amplifiers, high speed, high power, and microwave circuit applications.

Abstract (Chinese)
Abstract (English)
Chapter 1. Introduction……………………………….1

Chapter 2. Performance of InGaP/GaAs Single Delta-Doped High Electron Mobility Transistors
2-1. Introduction …………………………………4
2-2. Device Structures ……………………………5
2-3. Results and Discussion ..………………………6
2-4. Conclusions …..............................................12

Chapter 3. Performance of InGaP/GaAs Double Delta-Doped High Electron Mobility Transistors
3-1. Introduction ……………………………….….14
3-2. Device Structures ………………………….…15
3-3. Results and Discussion .…………………........16
3-4. Conclusions .………………………………….19
Chapter 4. Conclusion and Prospect
4-1. Conclusion ………………….…………………..20
4-2. Prospect …………………..….……….……….22
References ……………………………………………… ……….24
Tables
Figures

Table Lists
Table I Simulated results of the single delta-doped HEMTs.
Table II Simulated results of the double delta-doped HEMTs.

Figure Captions
Figure 2-1 The schematic cross section of the device A with upper
delta-doped sheet.
Figure 2-2 The schematic cross section of the device B with lower
delta-doped sheet.
Figure 2-3 (a) Corresponding energy-band diagrams of the device A at
equilibrium.
Figure 2-3 (b) The energy band diagrams along 2DEG channel from
source to drain region at equilibrium of the device A.
Figure 2-3 (c) The energy band diagrams along 2DEG channel from
source to drain region at VDS = 0.75 V of the device A.
Figure 2-4 Simulated electronic distribution of the device A at
equilibrium.
Figure 2-5 The simulated gate-to-drain current-voltage characteristic of
the device A.
Figure 2-6 Simulated drain-to-source current-voltage characteristics of
the device A. The controlled gate voltage is applied by +0.5
V/step.
Figure 2-7 Simulated drain-to-source saturation current and
transconductance versus the gate bias for the device A.
The drain-to-source voltage is fixed at +6 V.
Figure 2-8 Simulated output conductance versus the drain bias for the
device A. The gate-to-source voltage is fixed at +0.5 V.
Figure 2-9 Microwave performance of the device A.
Figure 2-10 Corresponding energy-band diagrams of device B at
equilibrium.
Figure 2-11 Simulated electron distribution of the device B at
equilibrium.
Figure 2-12 The simulated gate-to-drain current-voltage characteristic
of the device B.
Figure 2-13 Simulated drain-to-source current-voltage characteristics
of the device B. The controlled gate voltage is applied by
+0.5 V/step.
Figure 2-14 Simulated drain-to-source saturation current and
transconductance versus the gate bias for the device B.
The drain-to-source voltage is fixed at +6 V.
Figure 2-15 Simulated output conductance versus the drain bias for the
device B. The gate-to-source voltage is fixed at +0.5 V.
Figure 2-16 Microwave performance of the device B.
Figure 3-1 (a) Schematic cross section of the device C with double
delta-doped sheets. The top and bottom delta-doped
concentrations are of 2.5 × 1012 and 2.5 × 1012 cm-2,
respectively.
Figure 3-1 (b) Schematic cross section of the device D with double
delta-doped sheets. The top and bottom delta-doped
concentrations are of 1 × 1012 and 4 × 1012 cm-2,
respectively.
Figure 3-1 (c) Schematic cross section of the device E with double
delta-doped sheets. The top and bottom delta-doped
concentrations are of 4 × 1012 and 1 × 1012 cm-2,
respectively.
Figure 3-2 (a) Corresponding energy-band diagrams of the device C at
equilibrium.
Figure 3-2 (b) Corresponding energy-band diagrams of the device D at
equilibrium.
Figure 3-2 (c) Corresponding energy-band diagrams of the device E at
equilibrium.
Figure 3-3 (a) Simulated electron distribution of the device C at
equilibrium.
Figure 3-3 (b) Simulated electron distribution of the device D at
equilibrium.
Figure 3-3 (c) Simulated electron distribution of the device E at
equilibrium.
Figure 3-4 (a) The simulated gate-to-drain current-voltage characteristic
of the device C.
Figure 3-4 (b) The simulated gate-to-drain current-voltage characteristic
of the device D.
Figure 3-4 (c) The simulated gate-to-drain current-voltage characteristic
of the device E.
Figure 3-5 (a) Simulated drain-to-source current-voltage characteristics
of the device C. The controlled gate voltage is applied by
+0.5 V/step.
Figure 3-5 (b) Simulated drain-to-source current-voltage characteristics
of the device D. The controlled gate voltage is applied by
+0.5 V/step.
Figure 3-5 (c) Simulated drain-to-source current-voltage characteristics
of the device E. The controlled gate voltage is applied by
+0.5 V/step.
Figure 3-6 (a) Simulated drain-to-source saturation current and
transconductance versus the gate bias for the device C.
The drain-to-source voltage is fixed at +6 V.
Figure 3-6 (b) Simulated drain-to-source saturation current and
transconductance versus the gate bias for the device
D. The drain-to-source voltage is fixed at +6 V.
Figure 3-6 (c) Simulated drain-to-source saturation current and
transconductance versus the gate bias for the device E.
The drain-to-source voltage is fixed at +6 V.
Figure 3-7 (a) Simulated output conductance versus the drain bias for the
device C. The gate-to-source voltage is fixed at +0.5 V.
Figure 3-7 (b) Simulated output conductance versus the drain bias for the
device D. The gate-to-source voltage is fixed at +0.5 V.
Figure 3-7 (c) Simulated output conductance versus the drain bias for the
device E. The gate-to-source voltage is fixed at +0.5 V.
Figure 3-8 (a) Microwave performance of the device C.
Figure 3-8 (b) Microwave performance of the device D.
Figure 3-8 (c) Microwave performance of the device E.

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