跳到主要內容

臺灣博碩士論文加值系統

(44.221.70.232) 您好!臺灣時間:2024/05/30 20:03
字體大小: 字級放大   字級縮小   預設字形  
回查詢結果 :::

詳目顯示

: 
twitterline
研究生:彭信豪
研究生(外文):Hsin-Hao Peng
論文名稱:快速多輸入運算元之十進位加法器之設計與實作
論文名稱(外文):Design and Implementation of High-Speed Multi-operand Decimal Adders
指導教授:莊作彬
指導教授(外文):Tso-Bing Juang
學位類別:碩士
校院名稱:國立屏東商業技術學院
系所名稱:資訊工程系(所)
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2011
畢業學年度:99
語文別:中文
論文頁數:46
中文關鍵詞:超大型積體電路設計(VLSI Design)十進位加法計算機算術前綴平行加法器前瞻式進位加法器
外文關鍵詞:Computer arithmeticVLSI designParallel-prefix addersDecimal additionsCarry lookahead adders
相關次數:
  • 被引用被引用:0
  • 點閱點閱:384
  • 評分評分:
  • 下載下載:26
  • 收藏至我的研究室書目清單書目收藏:0
本篇論文中,我們提出了一個改善面積的三輸入十進位家法器,這個方法利用了分析電路及遞迴設計來產生補償值,為了減少面積及將輸入的位元提高,利用了序向電路來增加多輸入的運算,以完成多輸入的十進位加法的有效運算。

以三輸入的方式來合成,結果顯示我們所提出的三輸入十進位加法(方法1),與[26]的三輸入十進位加法在相同延遲時間(4-digit)的條件下,面積省了約47%。

以序向電路的方式來合成,結果顯示我們的多輸入十進位加法(方法2),與[26]的三輸入十進位加法在相同延遲時間的條件下,面積省了約30%。

除此之外,我們所測量的功率消耗與[9]的比較下也相對較低。而本篇論文所提出的多輸入十進位加法適用於大量的十進位計算。
In this paper, we have proposed area-efficient decimal adders with three inputs. By using proposed analyzer circuits and the generation of correction terms with recursive schemes, our proposed decimal adders could perform efficient summations with three inputs of operands. Synthesis shows that our proposed adders save up to 41.6 % area cost compared to previously reported decimal adders with three inputs under the same delay constraint. Besides that, the power consumptions for our decimal adders are lesser. Our proposed decimal adders could be applied to ease the tremendous computation efforts for decimal numbers.
目錄
1. 簡介 1
1.1 軟體簡介 2
1.2 相關應用 3
1.3 章節介紹 4
2. 傳統十進位加法介紹 5
3. 文獻回顧:Reduced BCD delay Adder 6
3.1 Reduced BCD delay Adder - Analyzer 7
3.2 Reduced BCD delay Adder - Carry Network 9
4. 三輸入運算元的十進位加法器設計 11
4.1 三輸入運算元十進位加法器設計 11
4.1.1 傳統三輸入運算元的十進位加法器設計 11
4.1.2 Reduced BCD delay Adder with Three Inputs 12
4.2 方法1 13
4.2.1 Area-Efficient Decimal Adder with Three Inputs 13
4.2.2 Area-Efficient Decimal Adder with Three Inputs - Analyzer 14
4.2.3 Area-Efficient Decimal Adder with Three Inputs – Carry Network 16
4.2.4 範例 18
4.3 方法2 19
4.3.1 Using CSA BCD Adder with Three Inputs 19
4.3.2 Using CSA BCD Adder with Three Inputs - Analyzer 20
4.3.3 Using CSA BCD Adder with Three Inputs – 化簡概念 21
4.3.4 Using CSA BCD Adder with Three Inputs – 化簡範例 22
4.3.5 範例 25
5. 方法3:序列數字之三輸入十進位加法設計 26
6. 比較與分析 29
6.1. 方法1比較 29
6.2. 方法2比較 34
6.3. 序向電路架構比較 36
7. 結論 37
參考文獻
[1]Draft IEEE Standard for Floating-Point Arithmetic. New York: IEEE, Inc., 2004, http://754r.ucbtest.org/drafts
[2]M. S. Schmookler and A.W.Weinberger. “High Speed Decimal Addition,” IEEE Transactions on Computers, Vol. 20, No. 8, pp. 862–867, Aug. 1971.
[3]M. A. Erle, M. J. Schulte, and J. M. Linebarger, “Potential speedup using decimal floating-point hardware,” Proc. of the Thirty-Sixth Asilomar Conference on Signals, Systems and Computers, Vol. 2, pp. 1073–1077, Nov. 2002.
[4]M. F. Cowlishaw, “Decimal Floating-Point: Algorism for Computers,” Proc. of 16th IEEE Symposium on Computer Arithmetic (ARITH-16), pp. 104–111, June 2003.
[5]R.D. Kenney and M.J. Schulte, “Multioperand Decimal Addition,” Proc. IEEE Computer Society Ann. Symp. VLSI, pp. 251-253, Feb. 2004.
[6]R.D. Kenney and M.J. Schulte, “High-speed multioperand decimal adders,” IEEE Transactions on Computers, pp. 953-963, Vol. 54, No. 8, Aug. 2005.
[7]Thapliyal, H, Kotiyal. S, Srinivas, M.B., “Novel BCD adders and their reversible logic implementation for IEEE 754r format”, Proc. 19th IEEE International Conference on VLSI Design, pp. 3-7, Jan. 2006
[8]Sreehari Veeramachaneni, M.Kirthi Krishna, Lingamneni Avinash, Sreekanth Reddy P, M.B. Srinivas, “Novel, High-Speed 16-Digit BCD Adders Conforming to IEEE 754r Format,” Proc. IEEE Computer Society Ann. Symp. VLSI (ISVLSI'07), pp. 343-350, May 2007.
[9]A. Bayrakci and A. Akkas, “Reduced delay BCD adder,” Proc. IEEE 18th International Conference on Application-specific Systems, Architectures and Processors, (ASAP), pp. 266-271, July 2007.
[10]G. Bioul, M. Vazquez, J. P. Deschamps, and G. Sutter, "Decimal addition in FPGA," Proc. SPL. 5th Southern Conference on Programmable Logic, pp. 101-108, 2009.
[11]A. Vazquez and E. Antelo, "A High-Performance Significand BCD Adder with IEEE 754-2008 Decimal Rounding," Proc. 19th IEEE Symposium on Computer Arithmetic (ARITH-19), pp. 135-144, 2009.
[12]E. Cornea, J. Harrison, J. C. Anderson, P. Tang, E. Schneider, and E. Gvozdev, "A Software Implementation of the IEEE 754R Decimal Floating-Point Arithmetic Using the Binary Encoding Format," IEEE Transactions on Computers, Vol. 58, No. 2, pp. 148-162, Feb. 2009.
[13]M.A. Erle and M.J. Schulte, “Decimal Multiplication via Carry-Save Addition,” Proc. IEEE 14th Int’l Conf. Application-Specific Systems, Architectures, and Processors, pp. 348-358, June 2003.
[14]M. A. Erle, E. M. Schwarz, and M. J. Schulte, "Decimal multiplication with efficient partial product generation," Proc. 17th IEEE Symposium on Computer Arithmetic (ARITH-17), pp. 21-28, 2005.
[15]M. A. Erle, M. J. Schulte and B. J. Hickmann, "Decimal Floating-Point Multiplication Via Carry-Save Addition," Proc. 18th IEEE Symposium on Computer Arithmetic (ARITH-18), pp. 46-55, 2007.
[16]B. J. Hickmann, A. Krioukov, A.M. J. Schulte and M. A. Erle, "A parallel IEEE P754 decimal floating-point multiplier," Proc. 25th International Conference on Computer Design (ICCD), pp. 296-303, 2007.
[17]G. Jaberipur, and A. Kaivani, "Binary-coded decimal digit multipliers," IET Computers & Digital Techniques, Vo1. 1, No. 4, pp. 377-381, 2007.
[18]A. Vazquez, E. Antelo and P. Montuschi, "A New Family of High Performance Parallel Decimal Multipliers," Proc. of the 18th IEEE Symposium on Computer Arithmetic (ARITH-18), pp. 195-204, 2007.
[19]R. K. James, T. K. Shahana, K. P. Jacob, and S. Sasi, "Decimal multiplication using compact BCD multiplier," Proc. International Conference on Electronic Design (ICED), pp. 1-6, 2008.
[20]G. Jaberipur and A. Kaivani, "Improving the Speed of Parallel Decimal Multiplication," IEEE Transactions on Computers, Vol. 58, No. 11, pp. 1539-1552, Nov. 2009.
[21]A. Vazquez, E. Antelo and P. Montuschi, "Improved Design of High-Performance Parallel Decimal Multipliers," IEEE Transactions on Computers, Vol. 59, No. 5, pp. 679-693, May 2010.
[22]H. Nikmehr, B. Phillips, and C. -C. Lim "Fast Decimal Floating-Point Division," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 14, No. 9, pp. 951-961, Sept. 2006.
[23]T. Lang, and A. Nannarelli, "Division Unit for Binary Integer Decimals," Prof. 20th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), pp. 1-7, 2009.
[24]T. Lang and A. Nannarelli, "A Radix-10 Digit-Recurrence Division Unit: Algorithm and Architecture," IEEE Transactions on Computers, Vol. 56, No. 6, pp. 727-739, June 2007.
[25]L. -K. Wang, M. A. Erle, C. Tsen, E. M. Schwarz and M. J. Schulte, "A survey of hardware designs for decimal arithmetic," IBM Journal of Research and Development, Vol. 54, Issue 2, pp. 8:1-8:15, 2010.
[26]P. Parhami, Computer Arithmetic: Algorithms and Hardware Designs. New York: Oxford Univ. Press, 2000.
[27]Tso-Bing Juang and Hsin-Hao Peng, "Area-Efficient Decimal Adders with Three Inputs," Proc. VLSI Design/CAD, pp. 478-451 , Aug. 2010. (Kaohsiung)
QRCODE
 
 
 
 
 
                                                                                                                                                                                                                                                                                                                                                                                                               
第一頁 上一頁 下一頁 最後一頁 top