臺灣博碩士論文加值系統

為了實現愈來愈複雜、以及更加有彈性的圖形呈像演算法，現今的設計傾向將微處理器核心整合進繪圖處理器以支援可程式化繪圖功能。然而，繪圖處理器中像素著色器的執行週期在不同應用上會不ㄧ樣，圖形繪圖流程中其餘固定功能由於很難評估產出率導致硬體實作變得較不簡單。此外，著色處理器與特定功能硬體模組間的資料傳輸也會讓系統效能降低許多；因此本論文著重在實現固定繪圖功能中的重要步驟「點陣化處理」，並提出由著色處理器執行的純軟體作法。純軟體的點陣化需要98個週期計算三角形前置設定，以及每筆像素13個週期左右的內插階段處理。為了進一步提升點陣化處理效能，本論文也提出改良的軟硬體設計－由一特殊的內嵌掃描轉換單元與著色處理器共同合作。此額外增設的單元佔8.5k的邏輯閘，約略是整個繪圖處理器的1.7%大小，但此硬體單元的增設在本論文測試項目－brick，可以比純軟體的作法減少約30%的執行週期。本論文尚實現了立體圖形呈像功能；為了提供立體效果，ㄧ般需要額外執行ㄧ次的繪圖流程以產生出不同視點下的結果，然而本論文額外加入ㄧ小段的程式碼讓像素著色器執行，以調整來自頂點著色器的水平座標，從而避免頂點著色器額外的繪圖動作。

In order to realize the advanced graphics rendering algorithms which tends to become more complex and flexible, more and more graphics processor units (GPU) include a micro-processor-like core to support the programmable shading capability. However, since the number of cycles spent in the fragment shader in programmable GPU will vary with different applications, the hardware implementation of the remaining fixed function of the graphics rendering flow becomes not trivial because the suitable target throughput is hard to set. In addition, the data transfer between the shader processor and other hardware fixed-function modules will also represent a big overhead. Therefore, this thesis focuses on realizing the rasterization, which is a very important fixed rendering function, and proposes a pure-software solution that can be executed by the shader processor. The pure-software rasterization requires 98 cycles in setup-stage, and an average of 13 cycles per pixel in interpolation-stage. To further accelerate this rasterization, this thesis also proposes an hardware-software codesign which uses a embedded scan-conversion unit to cooperate with the shader processor. This unit costs about 8.5K gates, which occupies only 1.7% of the entire GPU, but can help reduce more than 30% cycles compared with the pure-software approach in the test-benches used in this thesis. The other contribution of this thesis is to implement the stereoscopic graphic rendering function. To provide stereoscopic effect, the graphic rendering system has to run the entire rendering flow for additional passes to generate the results from different views. However, this thesis will embed an additional code in the fragement shader to adjust the x-coordinate position generated by vertex shader to avoid the additional running pass of the vertex shader.

論文審定書 i
中文摘要 ii
英文摘要 iii
第 一 章 概論 1
1.1研究動機 1
1.2論文大綱 2
第 二 章 研究背景 3
2.1三维繪圖流程介紹 3
2.2OpenGL ES介紹 4
2.2.1OpenGL ES 1.0 4
2.2.2OpenGL ES 2.0 9
2.3三角形前置設定介紹 12
2.4 點陣化簡介及相關探討 17
2.5 立體呈像介紹 25
2.5.1立體視覺成因 25
2.5.2視差 27
2.5.3立體顯示技術 28
第 三 章 三維圖形呈像引擎設計 30
3.1像素著色器之說明與架構 30
3.2三角形前置設定之設計與實作 33
3.3點陣化處理之實作 39
3.4支援使用者自定義屬性參數之硬體設計 42
第 四 章 點陣化加速電路設計 47
4.1掃描系統之介紹與分析 47
4.2點陣化掃描模組電路設計 53
第 五 章 低成本之立體呈像運算架構 61
第 六 章 系統實作結果 67
第 七 章 結論與未來目標 71
7.1結論 71
7.2未來目標 71
參考文獻 73
附錄一 三角形前置設定程式碼 75
附錄二 三角形前置設定之暫存器使用分配 79

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