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研究生:林宗正
研究生(外文):Tsung-Chen Lin
論文名稱:ARM10仿真器暨協同處理器的設計與驗證方法
論文名稱(外文):Design and Verification of ARM10 ICE Co-Processor
指導教授:黃英哲黃英哲引用關係
指導教授(外文):Ing-Jer Huang
學位類別:碩士
校院名稱:國立中山大學
系所名稱:資訊工程學系研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2011
畢業學年度:99
語文別:中文
論文頁數:108
中文關鍵詞:即時系統除錯靜態除錯嵌入式電路擬真器協同處理器微處理器
外文關鍵詞:CoprocessorEmbedded in circuit emulator (EICE)Real-time system debugMicroprocessorStatic Debug
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嵌入式電路擬真器(EICE)是目前微處理器最常見的也是最普遍使用的除錯技術。因為 ICE 本身可以提供良好的除錯與測試機制,例如:單步除錯(Single Step)、中斷點 (Breakpoint) 的設定與偵測、內部資源的監督與修改。

然而在傳統的嵌入式電路擬真器(EICE),在進行除錯時暫停處理器的運行,屬於靜態除錯 (Static Debug),缺點並無法對即時系統 (Real-time system)進行除錯。因此,提出不需要暫停微處理器的另一種除錯硬體-協同處理器Coprocessor14 (the Debug Coprocessor)具有可以在Run-time System下進行的除錯機制

本篇論文的主要針對在於將嵌入式電路擬真器(Embedded In-Circuit Emulator),結合Coprocessor 14來提供靜態除錯和即時系統除錯(Real-time system debug),結合CP14的除錯機制,我們在進行除錯時,不需再局限於使用IEEE 1149.1測試除錯通訊埠,來控制除錯硬體來除錯,也可以Program Level的方式,在程式中編入Coprocessor指令,設定除錯條件,觀察微處理器的內容。

Embedded in circuit emulator (EICE) is the most common and widely used debugging techniques for microprocessors. Because the ICE is capable to provide diverse debugging and testing mechanisms, such as: single-step debugging, breakpoints setting and detection, monitoring, and modification of internal resources.

However, the shortcoming of the conventional embedded in circuit emulator (EICE) is that the operation of the processor has to be suspended during debugging, which is categorized as static debugging (Static Debug) and is infeasible for real-time debugging. Therefore, this paper proposes a design alternative to support the real-time system debugging without suspending the microprocessor via the debug hardware Coprocessor14 (the Debug Coprocessor).

In this paper, the embedded in circuit emulator is combined with Coprocessor 14 to provide both the static debugging and Run-time system debugging. After incorporating CP14 with the debugging mechanism, the control of the debug hardware is no longer limited to use the IEEE 1149.1 test port during debugging. On the other hand, the set of debugging constraints and the observation of the internal state of the microprocessor can be achieved by inserting the Coprocessor instruction at the program level.

Chapter 1 Introduction 1
1.1 Background 1
1.2 Motivation 2
1.3 Proposed approach 3
1.4 Research contribution 4
Chapter 2 Related work 5
2.1 Traditional debug method 5
2.1.1 Simulator 5
2.1.2 Logic Analyzer 7
2.1.3 In Circuit Emulator 8
2.2 Embedded debug architecture 9
2.2.1 Embedded Real-Time Trace Circuit 9
2.2.2 Embedded In Circuit Emulator 10
Chapter 3 ARM10-ICE Architecture 16
3.1 Hardware Organization 16
3.1.1 Microprocessor Memory Architecture analysis 17
3.1.2 Scan chain Architecture analysis 18
3.1.3 JTAG Instruction and Coprocessor 14 instruction Analysis 19
3.1.4 Mode Switch Controlled 20
3.1.5 The Detail of Debug Component 21
3.1.6 The Signal between Coprocessor EICE and SYS32TMEIII 40
3.2 Debug Functionality 41
3.3 The protocol between the Coprocessor EICE and SYS32TMEIII 44
Chapter 4 Verification Strategy 46
4.1 JTAG-based Verification 46
4.1.1 Test Pattern 46
4.1.2 DBGTAP State Machine Functional Verification 49
4.1.3 Debug Control Registers Verification 50
4.1.4 Scan Chain Functional Verification 53
4.2 Coprocessor14 Verification 55
4.3 SYS32TMEIII Coprocessor EICE Verification 57
4.3.1 Coprocessor EICE Test Pattern 57
4.3.2 Program Level Verification 67
4.3.3 RTL Simulation Result 69
4.4 Gate Level Synthesis Result 72
Chapter 5 Conclusion 75
Chapter 6 Further work 76
Reference 77
Appendix A Related Files Structure 78
Appendix B Verilog Simulation of Task Module 79

Reference
[1] “The ARM1022E Technical Reference Manual”, Revision: r0p2, ARM Ltd., 2001
[2] “The ARM7TDMI Debug Architecture”, Application Note 28, Dec. 1995.
[3] “ARM7TDMI Data Sheet”, ARM Ltd., 1995.
[4] “The ARM Architecture Reference Manual” , ARM Ltd., 1996
[5] I. J. Huang, Tai-An Lu, ”ICEBERG: An Embedded In-circuit Emulator Synthesizer for Microcontrollers” Proc. of the 36’th Design Automation Conference, June 1998
[6] Ing-Jer Huang, Hsin-Ming Chen and Chung-Fu Kao, “Reusable embedded in-circuit emulator”, Design Automation Conference, pp. 33-34, 2001.
[7] Ing-Jer Huang, Chung-Fu Kao, Hsin-Ming Chen, Ching-Nan Juan and Tai-An Lu, “A retargetable embedded in-circuit emulation module for microprocessors” IEEE Design & Test of Computers, July-Aug. 2002, Volume 19 Issue 4, page 28 ~ 38
[8] Yuan-Long Jeang, Liang-Bi Chen, Yi-Ting Chou and Hsin-Chia Su, “An embedded in-circuit emulator generator for SOC platform” Proceedings IEEE International Conference on Field-Programmable Technology (FPT), 2003.
[9] Shyh-Ming Huang; Ing-Jer Huang; Chung-Fu Kao , “Reconfigurable real-time address trace compressor for embedded microprocessors”, Proceedings of IEEE International Conference on Field-Programmable Technology (FPT), Pages: 196- 203, 2003
[10] Dae-Young Jung, Sung-Ho Kwak and Moon-Key Lee, “Reusable embedded debugger for 32 bit RISC processor using the JTAG boundary scan architecture”, Proceedings 2002 IEEE Asia-Pacific Conference on ASIC Aug. 2002
[11] “IEEE Standard Test Access Port and Boundary-Scan Architecture”, IEEE Std. 1149.1-2001.
[12] NS Manju Nath, “On-chip debugging reaches a nexus”, EDN, May 11, 2000, page 95, http://www.edn.com/article/CA46888.html?text=on%2Dchip+and+debugging+and+reaches+and+a+and+nexus
[13] “IEEE-ISTO 5001™-1999, the Nexus 5001 Forum™ Standard for a Global EmbeddedProcessor Debug Interface”, Available at http://www.ieee-isto.org /Nexus5001.
[14] 陳柏舟, 應用於嵌入式電路擬真器之可參數化的軟硬體控制模組, 國立中山大學資訊工程研究所碩士論文, 2005
[15] 劉勇志, 八位元微控器之軟體開發環境及其擴充, 國立中山大學資訊工程研究所碩士論文, 2006
[16] ARM INC. ARM RVDEBUG V1.8 Application.
[17] 孫清華, JTAG測試原理與應用, 全華科技圖書股份有限公司, 1999
[18] “ARM11 MPCore Processor Technical Reference Manual”,ARM LTD.,2005
[19] Dae-Young Jung, Sung-Ho Kwak and Moon-Key Lee, “Reusable embedded debugger for 32 bit RISC processor using the JTAG boundary scan architecture”, Proceedings 2002 IEEE Asia-Pacific Conference on ASIC Aug. 2002

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