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研究生:郭冠甫
研究生(外文):Kuan-Fu Kuo
論文名稱:用於SoC整合之OCP-AHB Bus Interface發展
論文名稱(外文):OCP-AHB Bus Interface for SoC Integration
指導教授:黃英哲黃英哲引用關係
指導教授(外文):In-Jer Huang
學位類別:碩士
校院名稱:國立中山大學
系所名稱:資訊工程學系研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2011
畢業學年度:99
語文別:中文
論文頁數:102
中文關鍵詞:匯流排橋接介面系統單晶片整合三維圖形
外文關鍵詞:InterfaceBusSoCOCPIntegration
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IP (Intellectual Property)的重複使用率,在加速嵌入式系統開發的過程中,是一個重要且關鍵的因素,但不幸的是嵌入式系統環境的複雜性及差異性,又加深了IP重複使用的困難度,而本論文在於實作一個標準且一般化的的OCP-AHB匯流排介面架構,透過此匯流排介面可以讓符合OCP規範的IP,快速的連接到AMBA 2.0 AHB上,目的在於解決系統整合驗證時,因為不同環境、不同傳輸架構與IP之間相容性的問題,進而提高IP的重複使用率,並減少系統整合及驗證上所需花費的時間,除此之外IP設計者也可以專心於IP本身的設計。而此OCP-AHB匯流排介面根據輸出和輸入介面設計方式的不同,可以分成四種不同的版本,目的在於當IP和匯流排做資料傳輸時,能有更好的效能表現及較少的硬體成本,而此OCP-AHB匯流排介面架構實際應用於3D團隊所開發的三維圖形 (3D Graphics)加速處理器上。
A reliable scheme to reuse IP (Intellectual Property) cores became an important issue to accelerate the development of embedded systems. Unfortunately the diverse characteristic of embedded systems which deep the difficulty of IP reuse. This thesis proposed the OCP-AHB bus interface architecture by designing a standard and general interface. The IP cores with OCP interface can plug-an-play in bus quickly. It solve the environment problems of the diverse embedded systems and the compatibility issues between IP cores and on-chip interconnections, so the IP reuse ability are raised and the IP designer can focus only on their designs. There are four different versions of OCP-AHB bus interface according to the input and output interface designs. The porposed OCP-AHB bus interface has the better performance and small hardware area when IP transfer data each others through the bus. The result show the proposed architecture can reduce the system integration and verification time and the proposed architecture are actually use in three-dimensional graphics (3D Graphics) processor application.
Chapter 1. Introduction.................................................................1
1.1 Background ............................................................................1
1.2Motivation..................................................................................2
1.3 Research Methodology.........................................................3
1.4 Contribution ....................................................................................................4
Chapter 2. Related Works...........................................................................................5
2.1 My Research Tree ..........................................................................................5
Chapter 3. Review of Bus Interfaces ......................................................................12
3.1 Standard On-Chip Bus-Based Architecture ..................................................12
3.1.1 AMBA 2.0 Overview ........................................................................12
3.1.2 AMBA 3.0 Overview ........................................................................18
3.2 Socket-Based On-Chip Bus Interface Standards ..........................................22
3.2.1 OCP-IP Overview .............................................................................23
3.2.2 VCI Overview ...................................................................................29
Chapter 4. The Proposed OCP-AHB Bus Interface .............................................30
4.1 Introduction of OCP-AHB Interface ............................................................30
4.1.1 FSM-Based Architecture of OCP-AHB Interface .............................30
4.1.2 Basic OCP Signals Defined and Encoding .......................................32
4.1.3 OCP-AHB Master and Slave Interface FSM ....................................35
4.1.4 OCP-AHB Master and Slave Interface Circuit Structure .................43
4.2 Case Study ....................................................................................................46
4.2.1 Data Bandwidth Conversion .............................................................46
4.2.2 Interface with Register In/Out ..........................................................52
4.2.3 The Parameters of OCP-AHB Interface ............................................62
4.3 Verification Methodology of OCP-AHB Interface ......................................63
4.3.1 Standalone Verification Environment ...............................................63
4.3.2 Parameterized OCP-Scenario-Table (OST) ......................................65
4.3.3 A Unified RTL-SystemC-FPGA Verification Environment ..............67
4.3.4 Simulation Results of Standalone Verification .................................68
4.4 OCP Development Environment for IP Components ....................................72
4.5 Comparison and Analysis of OCP-AHB Interface ........................................74
4.5.1 Area Analysis ....................................................................................74
4.5.2 Timing Analysis ................................................................................75
4.5.3 Latency Analysis ...............................................................................76
Chapter 5. 3D Graphics OpenGL ES 2.0 Integration with OCP .........................79
5.1 3DG OpenGL ES 2.0 Introduction ..............................................................79
5.2 3DG OpenGL ES 2.0 Integrate with OCP Interface ....................................81
5.3 3DG OpenGL ES 2.0 Verification Environment ..........................................82
5.4 Simulation Results .......................................................................................83
5.5 Comparison ..................................................................................................86
Chapter 6. Conclusions and Future Work .............................................................87
6.1 Conclusions ..................................................................................................87
6.2 Future Work .................................................................................................88
Reference ...........................................................................89
Reference
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[2] Chih-Wea Wang, Chi-Shao Lai, Chi-Feng Wu, Shih-Arn Hwang, and Ying-His Lin, “On-Chip Interconnection Design and SoC Integration with OCP”, 13 Jun 2008, VLSI Dsign Automation and Test (VLSI-DAT)
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[9] Kenichiro Anjo, Atsushi Okamura and Masato Motomura, “Wrapper-Based Bus Implementation Techniques for Performance Improvement and Cost Reduction”, 04 May 2004, IEEE Journal of Solid-State Circuits (JSSC)
[10] Konstantinos Aisopos, Chien-Chun Chou and Li-Shiuan Peh, “Extending Open Core Protocol to Support System-Level Cache Coherence”, 2008, 6th International Conference on Hardware/Software Co-design and System Synthesis (IEEE / ACM / IFIP)
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[13] ARM, “AMBA Specification”, http://www.arm.com/
[14] OCP-IP, “Open Core Protocol Specification”, Available at http://www.ocpip.org/
[15] Sudeep Pasricha and Nikil Dutt, “On-Chip Commuincation Architecures (System on Chip Interconnect)”, 2008
[16] MDK-3D Fatchsheet, http://www.socle-tech.com/
[17]黃威晟“三維圖形加速系統單晶片之System/RTL/FPGA/Chip 均一化驗證方法 A Unified System/RTL/FPGA/Chip Verification Methodology for a 3D Graphics SoC” 國立中山大學碩士論文, 2008.
[18]林祺光“應用於OpenGL-ES 2.0 三維繪圖系統整合之非同步匯流排介面設計Asynchronous Bus Interface Design for OpenGL-ES 2.0 3D Graphics Systems” 國立中山大學碩士論文, 2011.
[19]陳立堯“支援浮點與定點格式運算可程式化頂點處理器之軟硬體整合Software and Hardware Integration of a Programable Floating and Fixed-Point Vertex Shader” 國立中山大學碩士論文, 2011.
[20]孫亞賢“低成本多執行緒之單一著色器架構設計Design of low-cost multi-thread unified shader architecture” 國立中山大學碩士論文, 2011.
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