臺灣博碩士論文加值系統

記憶體單元在現今的系統晶片 (system-on-chip ,SoC) 上所扮演的角色越來越重，並且佔去整體晶片中大部分的面積。雖然商業公司也會提供記憶體合成器，但通常都只提供了single-port與dual-port，而在SoC的設計上往往需要支援同時多個讀取與寫入，因此無法有效的使用在cell-based design flow。本論文將發展一個支援多讀寫的SRAM產生器，並且可產生在cell-based design flow上所需要使用到的檔案。使用商業公司的記憶體產生器要達到支援多讀寫必須複製dual-port的硬體來達到相應的功能，相較之下我們的SRAM產生器產生出的SRAM將會有較小的面積。此外我們還加入了一些低功率的設計，包括了電源閘控(power-gating)與本體偏壓(adaptive body-bias)。最後我們的多讀寫埠SRAM產生器將可產生一個低功耗、小面積的記憶體電路，並且可支援同時多讀取與寫入。

Memory unit is one of the fundamental hardware components in system-on-chip (SoC) design, and takes a significant portion of total area cost. Although commercial memory compilers exist, they usually contains memory unit with single-port or dual ports. However, many SoC designs require memory units that support simultaneous multiple reads and writes. They cannot be efficiently generated using the existing memory compilers in the standard cell library. In this thesis, we develop a memory generator that can automatically produce the circuits of multi-port SRAM and all the necessary models required in the standard cell-based design flow. Compared to the design based on dual-port SRAM from memory compilers which usually consists of duplicated copies of SRAM units for supporting multiple write at the same, the proposed design has smaller area cost. Furthermore, we employ various low-power design concepts, including power-gating and adaptive body-bias, to reduce the dynamic and static power of the generated SRAM circuits. Experimental results show that the proposed multi-port SRAM generator can be used to synthesize low-power and low-area register file circuits that support multiple reads and writes at the same time.

第1章 導論 1
1.1 研究動機 1
1.2 論文組織 2
第2章 靜態隨機存取記憶體與相關文獻 3
2.1 傳統靜態隨機存取記憶體架構 3
2.2 相關文獻 5
2.3 論文實作架構 10
第3章 多讀寫埠靜態隨機存取記憶體設計 12
3.1 靜態隨機存取記憶體細胞元設計 12
3.1.1 傳統6T靜態隨機存取記憶體細胞元設計 12
3.1.2 多讀寫埠記憶體細胞元設計 14
3.2 解碼電路設計 18
3.3 放大器電路設計 22
3.4 寫入電路設計 23
3.5 預先充電電路設計 24
3.6 局部位元線控制電路設計 24
3.7 降低漏電流設計 25
3.8 實作低功率的靜態隨機存取記憶體電路 26
第4章 多讀寫埠記憶體產生器實作 31
4.1 記憶體產生器簡介 31
4.2 產生器提供模組 35
4.2.1 Behavior Model 36
4.2.2 Synopsys Library Model 37
4.2.3 LEF Model 38
4.2.4 SPICE Netlist Model 39
4.2.5 Physical Layout Model 40
4.3 記憶體產生器時序介紹 41
第5章 模擬數據與比較 43
5.1 Pre-layout分析 43
5.2 Post-layout數據 45
第6章 未來展望 47
參考文獻 48

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