(3.237.20.246) 您好!臺灣時間:2021/04/16 08:24
字體大小: 字級放大   字級縮小   預設字形  
回查詢結果

詳目顯示:::

我願授權國圖
: 
twitterline
研究生:陳鉦欣
研究生(外文):Cheng-Hsin Chen
論文名稱:一無電容具中間隔離氧化層之垂直式單電晶體動態隨機存取記憶體之應用
論文名稱(外文):A Vertical Middle Partial Insulation Structure for Capacitorless 1T-DRAM Application
指導教授:林吉聰
指導教授(外文):Jyi-Tsong Lin
學位類別:碩士
校院名稱:國立中山大學
系所名稱:電機工程學系研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2011
畢業學年度:99
語文別:中文
論文頁數:75
中文關鍵詞:中間隔離氧化層垂直式電晶體資料保存時間浮體效應單電晶體無電容式動態隨機存取記憶體矽覆絕緣基板
外文關鍵詞:Floating Body EffectData Retention TimeMiddle Partial Insulation1T-DRAMVertical MOSFETSOI
相關次數:
  • 被引用被引用:0
  • 點閱點閱:101
  • 評分評分:系統版面圖檔系統版面圖檔系統版面圖檔系統版面圖檔系統版面圖檔
  • 下載下載:0
  • 收藏至我的研究室書目清單書目收藏:0
在本篇論文中,我們提出一新穎元件為具中間隔離氧化層(Middle Partial Insulation, MPI)之垂直式電晶體(Vertical Middle Partial Insulation, VMPI)應用在無電容式單電晶體動態隨機存取記憶體(Capacitorless One Transistor Dynamic Random Access Memory, 1T-DRAM),藉由TCAD的模擬輔助,我們比較VMPI元件與平面式中間隔離氧化層電晶體(Plane Middle Partial Insulation, PMPI)、傳統矽覆絕緣基板(Silicon on Insulate, SOI)元件等單體之性能,首先我們討論元件之基本電性,發現我們提出之VMPI元件較傳統SOI元件具有明顯的浮體效應(Floating body effect),有助於提升1T-DRAM的可程式規劃視窗(Programming Window),而在資料保存時間(Data Retention Time)的表現上,因為本體中性區的增加,加上中間隔離氧化層的輔助下,減少接面漏電流且降低電洞逸散機率,相較於傳統SOI元件皆有約5倍的效能提升;此外,因為VMPI元件為垂直式架構,除了增加本體中性區體積外,環繞式閘極(Gate-All-Around, GAA)結構對於資料的寫入能有更優秀的表現,這將對未來1T-DRAM提供一項極佳的解決方案。
In this thesis, we propose a novel vertical MOSFET device with middle partial insulator (MPI) or VMPI for capacitorless one transistor dynamic random access memory (1T-DRAM) application. In TCAD simulations, we compare the device performances of the planar MPI, conventional silicon-on-insulator SOI, and our proposed VMPI. Based on numerical simulation, we find out that the VMPI device has a large kink phenomenon for improving the programming window. As far as the data retention time is concerned, the hole carriers leaking into the source region are reduced due to the presence of a large pseudo neutral region and an effective blocking oxide layer. The retention time can thus be improved about 5 times when compared with conventional SOI counterpart. Furthermore, it should be noted that the gate-all-around (GAA) VMPI device structure not only increases the body pseudo-neutral region, but also enhances the 1T-DRAM performances, suggesting that the proposed VMPI can become a candidate for 1T-DRAM application.
第一章 導論 1
1.1 背景 1
1.2 論文回顧 4
1.3 動機 11
第二章 操作原理 12
2.1 運用機制 12
2.2 元件操作說明 13
第三章 元件製作 17
3.1 模擬元件 17
3.2 實作元件 19
第四章 研究方法與結果討論 21
4.1 研究方法 21
4.2 電性探討 23
4.2.1 元件架構說明 23
4.2.2 輸入與次臨界特性曲線 25
4.2.3 輸出特性曲線 28
4.3 1T-DRAM 應用探討 33
4.3.1 可程式規劃視窗 33
4.3.2 資料保存時間 43
4.3.3 元件容忍度 45
4.4 實作結果 48
第五章 結論與未來發展 52
5.1 結論 52
5.2 未來發展 52
參考文獻 53
個人著作 58
個人得獎相關文件 64


[1]Gordon Moore, “Cramming more components onto integrated circuits,” Proceedings of the IEEE, vol. 86, no.1, pp.82-85, Jan. 1998.
[2]D. H. Kim, J. Y. Kim, M. Huh, Y. S. Hwang, J. M. Park, D. H. Han, D. I. Kim, M. H. Cho, B. H. Lee, H. K. Hwang, J. W. Song, N. J. Kang, G. W. Ha, S. S. Song, M. S. Shim, S. E. Kim, J. M. Kwon, B. J. Park, H. J. Oh, H. J. Kim, D. S. Woo, M. Y. Jeong, Y. I. Kim, Y. S. Lee, H. J. Kim, J. C. Shin, J. W. Seo, S. S. Jeong, K. H. Yoon, T. H. Ahn, J. B. Lee, Y. W. Hyung, S. J. Park, H. S. Kim, W. T. Choi, G. Y. Jin, Y. G. Park and Kinam Kim, “A Mechanically Enhanced Storage node for virtually unlimited Height (MESH) Capacitor Aiming at sub 70nm DRAMs,”in IEDM Tech. Dig., Dec. 13-15, 2004, pp.69-72.
[3]H. Sunami, T. Kure, N. Hashimoto, K. Itoh, T. Toyabe, and S. Asai, “A Corrugated Capacitor Cell (CCC),”IEEE Trans. Electron Devices, vol. ED-31, no.6, pp.746-753, Jun. 1984.
[4]L. Nesbit, J. Alsmeier, B. Chen, J. DeBrosse, P. Fahey, M. Gall, J. Gambino, S. Gernhardt, H. Ishiuchi, R. Kleinhenz, J. Mandelman, T. Mii, M. Morikado, A. Nitayama, S. Parke, H. Wong, and G. Bronner, “A 0.6μm2 256Mb Trench DRAM Cell With Self-Aligned BuriEd STrap (BEST),” in IEDM Tech. Dig., Dec. 5-8, 1993, pp.627-630.
[5]D. Temmler, “Multilayer Vertical Stacked Capacitors (MVSTC) for 64Mbit and 256Mbit DRAMs,” in VLSI Symp. Tech. Dig., May 28-30, 1991, pp.13-14.
[6]T. Kaga, T. Kure, H. Shinriki, Y. Kawamoto, F. Murai, T. Nishida, Y. Nakagome, D. Hisamoto, T. Kisu, E. Takeda, and K. Itoh, “Crown-Shaped Stacked-Capacitor Cell for 1.5-V Operation 64-Mb DRAM’s,” IEEE Trans. Electron Devices, vol. 38, no.2, pp.255-261, Feb. 1991.
[7]A. Nitayama, Y. Kohyama, and K. Hieda, “Future Directions for DRAM Memory Cell Technology,” in IEDM Tech. Dig., Dec. 6-9, 1998, pp.355-358.
[8]S. W. Yang, W. S. Liao, L. Economikos, A. Guliani, D. Yang, B. Y. Kim, D. Dobuzinsky, and S. Shih, “Structural Demonstration of Cost Effective Isolation Trench Fill for Sub-ll0nm Vertical Trench DRAM and SOC Applications,” in Int. Symp. VLSI Tech. Sys. Appl., Oct. 6-8, 2003, pp.117-120.
[9]W. Mueller, G. Aichmayr, W. Bergner, M. Goldbach, T. Hecht, S. Kudelka, F. Lau, J. Nuetzel, A. Orth, T. Schloesser, A. Scholz, A. Sieck, A. Spitzer, M. Strasser, P. F. Wand, S. Wege, and R. Weis, “Trench DRAM Technologies for the 50nm Node and Beyond,” in Int. Symp. VLSI Tech. Sys. Appl., Apr. 24-26, 2006, pp.1-2.
[10]W. Mueller, G. Aichmayr, W. Bergner, E. Erben, T. Hecht, C. Kapteyn, A. Kersch, S. Kudelka, F. Lau, J. Luetzen, A. Orth, J. Nuetzel, T. Schloesser, A. Scholz, U. Schroeder, A. Sieck, A. Spitzer, M. Strasser, P-F. Wang, S. Wege, and R. Weis, “Challenges for the DRAM Cell Scaling to 40nm,” in IEDM Tech. Dig., Dec. 5-7, 2005, 4 pp. -339.
[11]Problem of stack capacitor and trench capacitor DRAM. [Online] Available : http://www.promos.com.tw/website/chinese/industrylist.jsp?id=1025056458566
[12]H.-J. Wann and C. Hu, “A Capacitorless DRAM Cell on SOI Substrate,” in IEDM Tech. Dig., Dec. 5-8, 1993, pp.635-638.
[13]S. Okhonin, M. Nagoga, J. M. Sallese, and P. Fazan, “A SOI Capacitor-less 1T-DRAM Concept,” in Proc. IEEE Int. SOI Conf., Oct. 1-4, 2001, pp.153-154.
[14]S. Okhonin, M. Nagoga, J. M. Sallese, and P. Fazan , “A Capacitor-less 1T-DRAM Cell,” IEEE Electron Device Lett., vol. 23, no.2, pp.85-87, Feb. 2002.
[15]P. Fazan, S. Okhonin, M. Nagoga, J. M. Sallese, L. Portmann, R. Ferrant, M. Kayal, M. Pastre, M. Blagojevic, A. Borschberg, and M. Declercq, “Capacitor-Less 1-Transistor DRAM,” in Proc. IEEE Int. SOI Conf., Oct. 7-10, 2002, pp.10-13.
[16]N. Collaert, M. Aoulaiche, M. Rakowski, B. De Wachter, K. Bourdelle, B.-Y. Nguyen, F. Boedta, D. Delprat, and M. Jurczak, “Analysis of sense margin and reliability of 1T-DRAM fabricated on thin-film UTBOX substrates,” in Proc. IEEE Int. SOI Conf., Oct. 5-7 2009, pp. 1-2.
[17]E. Yoshida, and T. Tanaka, “A capacitorless 1T-DRAM technology using gate-induced drain-leakage (GIDL) current for low-power and high-speed embedded memory,” IEEE Trans. Electron Devices, vol. 53, no. 4, pp. 692-697, Apr. 2006.
[18]J.-W. Han, S.-W. Ryu, S.-J. Choi, and Y.-K. Choi, “Gate-induced drain-leakage (GIDL) programming method for soft-programming-free operation in unified RAM (URAM),” IEEE Electron Device Lett., vol. 30, no. 2, pp. 189-191, Feb. 2009.
[19]S. Puget, G. Bossu, C. Fenouiller-Beranger, P. Perreau, P. Masson, P. Mazoyer, P. Lorenzini, J.-M. Portal, R. Bouchakour, and T. Skotnicki, “FDSOI floating body cell eDRAM using gate-induced drain-leakage (GIDL) write current for high speed and low power applications,” IEEE Int. Memory workshop, May 2009, pp. 1-2.
[20]K.-W. Song, H. Jeong, J.-W. Lee, S.I. Hong, N.-K. Tak, Y.-T. Kim, Y. L. Choi, H. S. Joo, S. H. Kim, H. J. Song, Y. C. Oh, W.-S. Kim, Y.-T. Lee, K. Oh, and C. Kim, “55 nm Capacitor-less 1T DRAM Cell Transistor with Non-overlap Structure,” in IEDM Tech. Dig., Dec. 15-17, 2008, pp.1-4.
[21]Z. Zhou, J. G. Fossum, and Z. Lu, “Physical Insights on BJT-based 1T DRAM Cells,” IEEE Electron Device Lett., vol. 30, no. 5, pp. 565-567, May 2009.
[22]J.-W. Han, D.-I. Moon, D.-H. Kim, and Y.-K. Choi, “Parasitic BJT read method for high-performance capacitorless 1T-DRAM mode in unified RAM,” IEEE Electron Device Lett., vol. 30, no. 10, pp. 1108-1110, Oct. 2009.
[23]S.-J. Choi, J.-W. Han,, D.-I. Moon, and Y.-K. Choi, “Analysis and evaluation of a BJT-based 1T-DRAM,” IEEE Electron Device Lett., vol. 31, no. 5, pp. 393-395, May 2010.
[24]G. Giusi, M. A. Alam, F. Crupi, and S. Pierro, “Bipolar Mode Operation and Scalability of Double-Gate Capacitorless 1T-DRAM Cells,” IEEE Trans. Electron Devices, vol. 57, no. 8, pp. 1743-1750, Aug. 2010.
[25]D.-I. Moon, S.-J. Choi, J.-W. Han, S. Kim, and Y.-K. Choi, “Fin-Width Dependence of BJT-Based 1T-DRAM Implemented on FinFET,” IEEE Trans. Electron Devices, vol. 31, no. 9, pp. 909-911, Sep. 2010.
[26]M. Aoulaiche, N. Collaert, R. Degraeve, Z. Lu, B.D. Wachter, G. Groeseneken, M. Jurczak, and L. Altimime, “BJT-Mode Endurance on a 1T-RAM Bulk FinFET Device,” IEEE Trans. Electron Devices, vol. 31, no. 12, pp. 1380-1382, Dec. 2010.
[27]M. Durlam, D. Addie, J. Akerman, B. Butcher, P. Brown, J. Chan, M. DeHerrera, B. N. Engel, B. Feil, G. Grynkewich, J. Janesky, M. Johnson, K. Kyler, J. Molla, J. Martin, K. Nagel, J. Ren, N. D. Rizzo, T. Rodriguez, L. Savtchenko, J. Salter, J. M. Slaughter, K. Smith, J. J. Sun, M. Lien, K. Papworth, P. Shah, W. Qin, R. Williams, L. Wise, and S. Tehrani, “A 0.18 μm 4Mb Toggling MRAM,” in IEDM Tech. Dig., Dec. 8-10, 2003, pp.34.6.1-34.6.3.
[28]Y. Asao, T. Kajiyama, Y. Fukuzumi, M. Amano, H. Aikawa, T. Ueda, T. Kishi, S. Ikegawa, K. Tsuchida, Y. Iwata, A. Nitayama, K. Shimura, Y. Kato, S. Miura, N. Ishiwata, H. Hada, S. Tahara, and H. Yoda, “Design and Process Integration for High-Density, High-speed, and Low-Power 6F2 Cross Point MRAM Cell,” in IEDM Tech. Dig., Dec. 13-15, 2004, pp.571-574.
[29]D. Ha and K. Kim, “Recent Advances in High Density Phase Change Memory (PRAM),” in Int. Symp. VLSI Tech. Sys. Appl., Apr. 23-25, 2007, pp.1-4.
[30]L. Perniola, V. Sousa, A. Fantini, E. Arbaoui, A. Bastard, M. Armand, A. Fargeix, C. Jahan, J.-F. Nodin, A. Persico, D. Blachier, A. Toffoli, S. Loubriat, E. Gourvest, G. B. Beneventi, H. Feldis, S Maitrejean, S Lhostis, A Roule, O. Cueto, G. Reimbold, L. Poupinet, T. Billon, B. D. Salvo, D. Bensahel, P. Mazoyer, R. Annunziata, P. Zuliani, and Fabien Boulanger, “Electrical Behavior of Phase-Change Memory Cells Based on GeTe,” IEEE Electron Device Lett., vol. 31, no. 5, pp. 488-490, May 2010.
[31]H.-J. Wann and C. Hu, “A capacitorless DRAM cell on SOI substrate,” in IEDM Tech. Dig., Dec. 5-8, 1993, pp. 635-638.
[32]E. Yoshida and T. Tanak, “A Design of a Capacitorless 1T-DRAM Cell Using Gate-induced Drain Leakage (GIDL) Current for Low-power and High-speed Embedded Memory,” in IEDM Tech. Dig., Dec. 8-10, 2003, pp. 37.6.1-37.6.4.
[33]M. G. Ertosun, H. Cho, P. Kapur, and K. C. Saraswa, “A Nanoscale Vertical Double-Gate Single-Transistor Capacitorless DRAM,” IEEE Electron Device Lett., vol. 29, no. 6, pp. 615-617, May 2008.
[34]S. Okhonin, M. Nagoga, E. Carman, R. Beffa, E. Faraon, “New Generation of Z-RAM,” in IEDM Tech. Dig., Dec. 10-12, 2007, pp. 925-928.
[35]E. X. Zhang, D. M. Fleetwood, F. El-Mamouni, M. L. Alles, R. D. Schrimpf, W. Xiong, C. Hobbs, K. Akarvardar, and Sorin Cristoloveanu, “Total Ionizing Dose Effects on FinFET-Based Capacitor-Less 1T-DRAMs,” IEEE Trans. Nuclear Science, vol. 57, no. 6, pp. 3298-3304, Dec. 2010.
[36]M. G. Ertosun, K.-Y. Lim, C. Park, J. Oh, P. Kirsch, and K. C. Saraswat, “Novel Capacitorless Single-Transistor Charge-Trap DRAM (1T CT DRAM) Utilizing Electrons,” IEEE Electron Device Lett., vol. 31, no. 5, pp. 405-407, May 2010.
[37]H. Liu, Z. Xiong, and J. K. O. Sin, “An Ultrathin Vertical Channel MOSFET for Sub-100-nm Applications,” IEEE Trans. Electron Devices, vol. 50, no. 5, pp. 1322-1327, May 2003.
[38]H. Cho, P. Kapur, P. Kalavade, and K. C. Saraswat, “A Low-Power, Highly Scalable, Vertical Double-Gate MOSFET Using Novel Processes,” IEEE Trans. Electron Devices, vol. 55, no. 2, pp. 632-639, Feb. 2008.
[39]J.-Y. Choi, and J. G. Fossum, “Analysis and Control of Floating-Body Bipolar Effects in Fully Depleted Submicrometer SOI MOSFET’s,” IEEE Trans. Electron Devices, vol. 38, no. 6, pp. 1384-1391, Jun. 1991.
[40]M. Valdinoci, L. Colalongo, G. Baccarani, G. Fortunato, A. Pecora, and I. Policicchio, “Floating Body Effects in Polysilicon Thin-Film Transistors,” IEEE Trans. Electron Devices, vol. 44, no. 12, pp. 2234-2241, Dec. 1997.
[41]J. P. Colinge, “Reduction of Kink Effect in Thin-Film SOI MOSFET’s,” IEEE Trans. Electron Devices, vol. 9, no. 2, pp. 97-99, Feb. 1988.
[42]J.-Y. Choi, and J. G. Fossum, “Analysis and Control of Floating-Body Bipolar Effects in Fully Depleted Submicrometer SOI MOSFET’s,” IEEE Trans. Electron Devices, vol. 38, no. 6, pp. 1384-1391, Jun. 1991.
[43]T. Hoffmann, G. Doornbos, I. Ferain, N. Collaert, P. Zimmerman, M. Goodwin, R. Rooyackers, A. Kottantharayil, Y. Yim, A. Dixit, K. D. Meyer, M. Jurczak and S. Biesemans, “GIDL (Gate-Induced Drain Leakage) and Parasitic Schottky Barrier Leakage Elimination in Aggressively Scaled HfO2/TiN FinFET Devices,” in IEDM Tech. Dig., Dec. 5-7, 2005, pp. 725-728.
[44]ISE TCAD 10.0, User’s Manual.
[45]D.-I. Bae, S. Kim, and Y.-K. Choi, “Low-Cost and Highly Heat Controllable Capacitorless PiFET (Partially Insulated FET) 1T DRAM for Embedded Memory,” IEEE Trans. On Nanotechnology, Vol. 8, no. 1, pp. 100 - 105, Jan. 2009.

QRCODE
 
 
 
 
 
                                                                                                                                                                                                                                                                                                                                                                                                               
第一頁 上一頁 下一頁 最後一頁 top
系統版面圖檔 系統版面圖檔