本論文主要提出一種直接數位頻率合成器 (direct digital frequency synthesizer，DDFS)改良架構，利用校正塊來簡化線性插值 (linear interpolation) 的硬體複雜度。校正塊主要來補償線性插值DDFS所產生的誤差曲線。由這些誤差曲線的圖形分析，得知每段誤差曲線存在一定的相似性，所以只要模擬出其中一段的誤差曲線，其他的誤差曲線可由模擬出的這一段經過固定比例的縮放。因此利用上述方式的校正塊，可以大約改善12分貝的雜波頻率動態範圍 ( spurious frequency dynamic range，SFDR)。
在設計過程中，以80分貝的SFDR為目標，然後確定每個方塊所需的最少的位元數。在一般分段線性插值DDFS的設計中，理論上需要有32段的分段線性插值來達到84分貝的SFDR。所以本論文用16段的分段線性插值加上提出的校正塊，來達到所訂目標的SFDR。晶片的模擬設計採用TSMC 0.13um 1P8M CMOS製程，其電路核心面積為78.11 x 77.49 um2。

In this thesis, a linear interpolation direct digital frequency synthesizer (DDFS) with improved structure to simplify the hardware complexity by correction block is proposed. Correction block is mainly used to compensate for the error curve of linear interpolation DDFS. From the analysis of these error curves, these error curves have similar behavior between each others. After selecting an error curve, the other error curves can be derived and multiplied by a fixed scale. From the simulation results, the correction block using the above method can improve about 12 dB spurious frequency dynamic range (SFDR).
The goal of the DDFS designed in this thesis is to achieve 80 dB SFDR. Minimum required number of bits for each block in the proposed DDFS is carefully selected by simulation. In general, DDFS with piecewise linear interpolation theoretically needs 32 segments of piecewise linear interpolation to achieve 84 dB SFDR. In this thesis, 16 segments of piecewise linear interpolation with correction block can achieve the target SFDR. The chip’s simulation is implemented by TSMC standard 0.13um 1P8M CMOS process with core area 78.11 x 77.49 um2.

誌 謝 ii
摘 要 iii
Abstract iv
目 錄 v
圖 次 vii
表 次 ix
第一章 簡介 1
第二章 基於線性插值的直接數位頻率合成器 4
2.1 線性插值的基本架構 4
2.1. 1 一般的系統架構 4
2.1. 2 最小平方法 ( Least Square Method ) 6
2.1. 3 八段線性插值的相位對振幅轉換器 7
2.2 分段線性插值的段數與SFDR的關係 8
2.2. 1 利用傅利葉級數分析輸出的頻譜 8
2.2. 2 分段數與SFDR的關係 9
第三章 提出校正塊的直接數位頻率合成器 12
3. 1 具有相似曲線的分段誤差 12
3. 2 校正塊的更正能力 15
第四章 系統模擬與晶片設計 17
4.1系統模擬 17
4.1.1 浮點數 (Floating Point) 的系統模擬 18
4.1.2 定點數 (Fixed Point) 的系統模擬 20
4. 2 晶片設計 23
4.2.1 ModelSim模擬驗證 24
4.2.2 Design Vision邏輯合成 26
4.2.3 SOC Encounter佈局與繞線 29
第五章 結論 30
參考文獻 32

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