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研究生:盧冠佑
研究生(外文):Kuan-Yu Lu
論文名稱:一新穎具有共享摻雜區域之高集積密度互補式金氧半反向器
論文名稱(外文):A Novel High Integration-Density CMOS Inverter with Unique Shared Contact
指導教授:林吉聰
指導教授(外文):Jyi-Tsong Lin
學位類別:碩士
校院名稱:國立中山大學
系所名稱:電機工程學系研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2011
畢業學年度:99
語文別:中文
論文頁數:127
中文關鍵詞:互補式金氧半反向器穿隧場效電晶體超薄本體矽覆絕緣無接面金氧半場效電晶體閘極控制之N-I-P電晶體
外文關鍵詞:TFETJL MOSFETUTBSOICMOSGated N-I-P transistor
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一種具有高集積密度、製程步驟簡單之新穎互補式金氧半(Novel CMOS)反向
器已經被發展出來,此種新穎互補式金氧半反向器是利用閘極控制之N-I-P 電晶體
(Gated N-I-P transistor)取代原本傳統互補式金氧半(CMOS)反向器之正型金氧半場
效電晶體(PMOSFET)負載器,以解決因為寬度補償做造成的集積密度降低的問題。
由於閘極控制之N-I-P 電晶體,其獨特的摻雜結構與輸出電流隨著閘極偏壓增加而
降低的特性,有利於當作邏輯閘之負載器,並搭配上不同種類之驅動器,如:負
型金氧半場效電晶體(NMOSFET)、負型穿隧場效電晶體(NTFET)或超薄本體(UTB)
之無接面金氧半場效電晶體(JL NMOSFET)…等,構成具獨特共享摻雜區域(N-type)
與共享輸出節點之新穎互補式金氧半反向器。本研究主要探討由負型穿隧場效電
晶體及超薄本體無接面金氧半場效電晶體當作驅動器,並以閘極控制N-I-P 電晶體
當作負載器之新穎互補式金氧半反向器及其特性與分析。根據結果,本研究所提
出之新穎互補式金氧半反向器有正確的邏輯特性,且延遲時間較互補式穿隧場效
電晶體(CTFET)改善了87.2 %,也較無接面互補式金氧半反向器(JL CMOS)改善了
43.2 %,這是因為閘極控制之N-I-P 電晶體其獨特操作機制且為雙載子傳輸的緣故。
此外,由於驅動器與負載器兩元件之間的摻雜區域(同為N-type)相同,可共享形成
輸出端,且為矽覆絕緣(SOI)結構,兩元件之間無須物理性隔離結構,可以大幅提
升集積密度,佈局面積較傳統互補式金氧半反向器節省54.1 %,較矽覆絕緣互補
式金氧半反向器節省40.1 %,並降低製程步驟。因此,我們相信,本研究所提出
之具高集積密度、製程步驟簡易之新穎互補式金氧半反向器可以成為未來下世代
互補式金氧半反向器的最佳候選之一。
A novel CMOS inverter has been proposed. We utilize gated N-I-P transistor to
replace the conventional PMOSFET for solving the problem of width compensation.
Also, we carefully investigate and analyze the non-conventional CMOS characteristics
with NTFET and/or UTB JL MOSFET as driver and gated N-I-P transistor as a load.
According to the results, our proposed novel CMOS inverter has correct logic behavior
and its delay time is reduced about 87.2 % when compared with the CTFET. Also, our
proposed CMOS still can get a 43.2 % reduction in delay time when compared with JL
CMOS. In addition, because of the N-type output drain node and the SOI structure, our
proposed CMOS does not need any physical isolation technique, thereby improving the
packing density. Our proposed CMOS indeed obtain a 54.1 % reduction of the total area
compared with the conventional CMOS. Our proposed CMOS also can achieve a 40.1
% reduction in the total area when compared with the SOI-based CMOS. More
importantly, due to the reduced process steps, the cost reduction can be achieved. We
therefore believe that a high packing density novel CMOS inverter with reduced process
steps can become one of the contenders for future CMOS scaling.
第一章 導論 1
1.1 背景 1
1.1.1 改變結構 3
1.1.2 改變材料 10
1.1.3 使用應力技術 13
1.2 動機 17
第二章 物理機制與元件操作原理 19
2.1 物理機制 19
2.1.1 穿隧場效電晶體(TFET)物理與操作機制 19
2.1.2 無接面負型金氧半場效電晶體(JL NMOSFET)物理與操作機制 21
2.1.3 閘極控制N-I-P電晶體(Gated N-I-P Transistor)物理與操作機制 22
2.2 新穎邏輯元件操作理論與原理 25
2.2.1. 傳統互補式金氧半邏輯閘操作理論與原理 25
2.2.2. 以負型穿隧場效電晶體及閘極控制N-I-P電晶體所構成之新穎具共享摻雜區域互補式金氧半反相器 29
2.2.3. 以無接面負型金氧半場效電晶體當作驅動器以及以閘極控制N-I-P電晶體當作負載器構成之新穎具共享摻雜區域與超薄本體互補式金氧半邏輯閘 31
第三章 元件架構設計與製作 37
3.1 元件架構設計 37
3.1.1 以負型穿隧場效電晶體及閘極控制N-I-P電晶體所構成之新穎具共享摻雜區域互補式金氧半反相器 37
3.1.2 由無接面負型金氧半場效電晶體及閘極控制N-I-P電晶體所構成,具有超薄本體結構與共享摻雜區域之新穎互補式金氧半反相器 46
第四章 結果與討論 49
4.1 元件模擬之物理模型 49
4.2 電性分析與討論 51
4.2.1 以負型穿隧場效電晶體及閘極控制N-I-P電晶體所構成之新穎具共享摻雜區域互補式金氧半反相器 51
4.2.2 由無接面負型金氧半場效電晶體及閘極控制N-I-P電晶體所構成,具有超薄本體結構與共享摻雜區域之新穎互補式金氧半反相器 65
4.3 基本邏輯電路模擬 69
4.3.1 反或閘 (NOR Gate) 69
4.3.2 反及閘 (NAND Gate) 75
4.3.3 環形震盪器(Ring Oscillator) 82
4.4 實作結果 84
第五章 新穎互補式金氧半反向器之優點 85
5.1 載子遷移率與延遲時間 85
5.2 製程步驟與集積密度 88
第六章 結論與未來展望 93
6.1 結論 93
6.2 未來展望 94
參考文獻 95
附錄 101
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