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研究生:戴志軒
研究生(外文):Chih-Hsuan Tai
論文名稱:具高微縮性的新穎無接面垂直式金氧半場效電晶體之短通道效應及射頻/類比性能探討
論文名稱(外文):Investigate Short-Channel Effects and RF/analog Performance of A Highly Scaled-Down Novel Junctionless Vertical MOSFET
指導教授:林吉聰
指導教授(外文):Jyi-Tsong Lin
學位類別:碩士
校院名稱:國立中山大學
系所名稱:電機工程學系研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2011
畢業學年度:99
語文別:中文
論文頁數:80
中文關鍵詞:矽覆絕緣汲極引致能障下降次臨界擺幅雙閘極自我加熱效應
外文關鍵詞:SOIjunctionlessshort-channel effectsDrain-Induced barrier lowering (DIBL)Subthreshold Swing (S.S.)double-gate
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本論文研究無接面垂直式電晶體的電性表現,並將其與無接面平面式電晶體和傳統垂直式場效電晶體做比較,分別探討雙閘極架構的優勢,以及無接面電晶體在短通道特性的表現;根據二維模擬結果,無接面垂直式電晶體因為雙閘極架構,相對於平面式電晶體有較好的短通道性能表現,次臨界擺幅和汲極引致能障下降的數據,無接面垂直式電晶體分別為62.04 mV/dec和23.96 mV/V,而無接面平面式電晶體為77.67 mV/dec和146.07 mV/V,證實雙閘極架構有較好的通道控制能力,且無接面垂直式電晶體可製作於矽基板上,更進一步免除使用矽覆絕緣基板所帶來之自我加熱效應,並降低生產成本;另外在無接面垂直式電晶體和傳統垂直式場效電晶體的短通道性能比較中,當柱狀主動區厚度逐漸微縮,傳統垂直式場效電晶體的次臨界擺幅和汲極引致能障下降都是呈現上升的情況,而無接面垂直式電晶體則是呈現下降的情形,說明元件微縮對無接面垂直式電晶體有性能提升的幫助;然而,雖然在射頻卅類比等特性方面,無接面垂直式電晶體略輸於傳統垂直式場效電晶體,但無接面垂直式電晶體製程簡單的優點,使其有機會成為未來半導體製程的主流技術。
In this thesis, we carefully investigate the electrical characteristics of junctionless vertical MOSFET (JLVMOS) compared with the junctionless planar MOSFET (JLPMOS) and conversional junction vertical MOSFET (JVMOS). Also, we examine the advantages of the double-gate structure and the short-channel behavior of the junctionless transistors. According to the 2D simulation studies, the proposed JLVMOS can achieve better short-channel characteristics (JLVMOS: 62.04 mV/dec S.S., 23.96 mV/V DIBL; JLPMOS: 77.67 mV/dec S.S., 146.07 mV/V DIBL) as compared with the planar transistor, chiefly owing to the double-gate scheme. This proves that only the double-gate device has better gate controllability over the channel region to reduce the short-channel effect. More importantly is that the JLVMOS has a bulk Si starting material, in which the SOI-induced self-heating effects and the fabrication cost can be well suppressed and reduced, respectively. In comparison with the JVMOS, our proposed JLVMOS exhibits better S.S. and reduced DIBL. Furthermore, although the analog/RF properties of the JLVMOS are somewhat degraded, due to its simple fabrication process, our proposed JLVMOS can become one of the mainstream technology for future CMOS applications.
第一章 緒論 1
1.1 背景 1
1.2 論文回顧 2
1.2.1 垂直式金氧半場效應電晶體 2
1.2.2 無接面金氧半場效應電晶體 5
1.3 結論與動機 10
第二章 元件設計與製程 11
2.1 元件操作原理 11
2.2 FLOOPS TCAD模擬元件理想製程 15
2.3 無接面垂直式電晶體(JLVMOS)實際製程 17
第三章 結果與討論 21
3.1 DESSIS物理模型說明 21
3.2 ISE TCAD模擬軟體DESSIS工具之元件性能分析 23
3.2.1 無接面垂直式和平面式電晶體結果分析 23
3.2.2 無接面和傳統場效垂直式電晶體結果分析 32
3.2.3 下方汲極之無接面和傳統場效垂直式電晶體結果分析 43
3.3 無接面垂直式電晶體實作結果 56
第四章 結論與未來發展 58
4.1 結論 58
4.2 未來發展和應用 58
參考文獻 59
附錄 63
個人著作 63
共同著作 64
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